The Low Latency Interface WG was created to build a specification before the end of 2010. It is composed of members from more than 10 companies that are contributing to the specification definition and 7 members who are contributing to the specification writing. The goal of the team is to produce a specification for an interface with sufficient performance to allow sharing a DRAM memory between 2 chips for data and program. The main motivation is EBoM cost reduction.
 

The second motivation is to give to LLI the capability to connect a companion chip and an APE and exchange transactions without SW intervention. This enables remote configuration and memory mapped transfers as if the 2 chips were a single chip.

The group was created from the LLI Investigation group that worked from November 2009 until March 2010 collecting the requirements from the industry and investigating the feasibility of the LLI interface.
 

The LLI specification defines several logical layers to help to make the specification more understandable:

• Transaction layer: exchanges memory mapped read/write transactions and signals between 2 chips.
• Data link layer: provides several independent virtual channels between the 2 chips.
• PHY adapter layer: provides an interface to the physical media. Focus first on serial MIPI MPHY. Ensure reliability as necessary.
• Power management. Interface control for optimal power consumption; definition of the power states.
• Boot and reset
• Test
   

 The group is currently defining:

• The PHY Adapter targeting low latency wakeup and low power consumption.
• The power modes and the mechanisms to transition between them.
• The Reset scheme.
   

History and Roadmap

Working Group Chair

Eric Badi, Texas Instruments

Working Group Vice-Chair

Christophe Avoinne, Texas Instruments

Member companies represented:

Analog Devices, ARM, Arteris, Broadcom, Cadence, Infineon, MCCI, Micron, Motorola, Nokia, Qualcomm, RIM, SMSC, ST, STE, TI.