The Low Latency Interface (LLI) Working Group (WG) was created in 2010. The WG was created from the LLI Investigation Group (IG) that worked from November 2009 until March 2010 collecting requirements from the industry, investigating the feasibility of the new interface, and developing a WG charter. The main focus of the WG is to define a point-to-point interconnect between the application processor and the modem/baseband processor with sufficient performance to allow sharing of DRAM memory between 2 chips for data and program. A primary motivation is EBoM cost reduction, in addition to the capability of connecting a companion chip to an APE and exchange transactions without SW intervention, thus enabling remote configuration and memory mapped transfers as if the 2-chips were a single-chip.
The WG published the MIPI® Alliance Specification for Low Latency Interface (LLI) v0.8 in August 2011, and the MIPI Alliance Specification for Low Latency Interface (LLI) v1.0 in April 2012. The WG also released Frequently Asked Questions (FAQ) for LLI v1.0 as a supporting document for implementers.
The WG is currently working on the MIPI Alliance Specification for Low Latency Interface (LLI) Version v2.0. This document is being developed to offer new extensions and to improve efficiency and is scheduled for release to MIPI Members in Q2 2013. The WG is also developing a new Application note for IPC over LLI to be release with the LLI v2.0 Specification.
|LLI Investigation Group Created||Nov ‘09|
|Charter Approved by MIPI BoD||Mar ‘10|
|LLI Working Group Established||Mar ’10|
|LLI Specification v0.80 Approved||Aug ’11|
|LLI Specification v1.0 Approved||Apr ‘12|
|LLI FAQ v1.0 Published||Apr ‘12|
|LLI Specification v2.0 Estimated Approval/Publication||Apr '13|
|Application Note for IPC over LLI Estimated Approval/Publication||Apr '13|
|LLI FAQ v2.0 Estimated Approval/Publication||
Interim Chair: Bipin Balakrishnan, ST Ericsson