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The PHY Working Group is chartered to specify high-speed physical layer designs to support multiple application requirements. The first specification developed by the PHY WG was targeted primarily to support the requirements of camera and display applications. The resulting standard, D-PHY, is a low-power, differential signaling solution with a dedicated clock lane and one or more (scalable) data lanes. In addition to supporting MIPI
The physical layer, or PHY, is the heart of any advanced, serial interconnect standard. Very different peripherals often share similar requirements at the PHY level. Recognizing this, MIPI® developed a single D-PHY specification as a re-usable physical layer solution upon which MIPI camera interfaces, display panel interfaces, and general-purpose high-speed/low-power interfaces could be based. This helped streamline the development of multiple standards in MIPI, but also benefits the companies implementing these interfaces in semiconductor products, since much of the PHY engineering investment can be re-used on subsequent designs.
MIPI D-PHY delivers up to 1.5 Gbps per lane via an advanced source-synchronous, differential SLVS design which is scalable to the number of lanes required by the application. It meets the demanding requirements of low-power, low-noise-generation, and high-noise immunity which mobile phone designs demand.
The PHY Working Group has successfully launched M-PHY v2.0, the next step in the GEAR roadmap, with bandwidth speeds reaching 2.9Gbps per lane. The group continues its work on M-PHY to increase high speed bandwidth and anticipates that next generation versions will be available in 2013.
MIPI M-PHY is a high-frequency, low-power physical layer defined by MIPI AllianceSpecification for M-PHYSM. . The M-PHY can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and communication between Baseband and RFIC. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
It currently supports or will support the following MIPI Specifications: DigRF v4,
Please refer to the evolution graph for more information about the status.
Ken Drottar, Intel
Working Group Vice-Chairs
Andrew Baldman, UNH-IOL
Henrik Icking, Intel Corporation
Raj Kumar Nagpal, STMicroelectronics