MIPI White Paper:
Making the 5G Vision a Reality
A 5G Readiness Assessment of MIPI Specifications
3 MIPI Specifications are 5G Ready
This section reviews the MIPI interface specifications that a typical high-end 4G LTE smartphone currently uses (Note: MIPI has other specifications, but only those most applicable to 5G readiness are discussed in this paper). In mid-2018, several major vendors had begun using MIPI specifications for their initial 5G smartphones. This section also discusses the MIPI Alliance roadmap for providing additional features to further enhance the performance and user experience to meet the next phase of 5G requirements.
3.1 How MIPI Interfaces Enable 5G Smartphones
The first wave (phase 1) of high-end 5G smartphones is expected to be an enhancement of the high-end 4G devices currently on the market. Major enhancements will include the addition of the new 5G NR RF subsystem, and the evolution of other subsystems to enable better user experiences and richer multimedia capabilities. For example, these 5G smartphones may have three to four high-resolution rear cameras with high-frame-rate/slow-motion video capture capability, an enhanced microphone array, multi-channel audio and stereo speakers.
The 5G modem and application processor use MIPI specifications such as CSI-2 for cameras and DSI-2 for the display, as well as either the low-power, high-bandwidth, pin-efficient MIPI D-PHY or C-PHY physical layers. MIPI RFFE for RF front-end devices control, and MIPI UniPro with M-PHY for high-performance flash storage are all becoming ubiquitous in 5G designs. MIPI I3C, SoundWire, SLIMbus and upcoming VGI specifications are expected to be adopted in many upcoming 5G smartphone platforms as well.
Table 1 summarizes the MIPI specifications, whose features, advantages, 5G phase 1 readiness and future roadmap plans are discussed later in this section.
3.1.1 MIPI SLIMbus and SoundWire: Rich, Immersive Audio and
The MIPI Audio Working Group defines two specifications: MIPI SLIMbus and MIPI SoundWire. These interfaces simplify the integration of multiple audio components in a wide range of platforms, including smartphones, PCs, connected vehicles, wearables and IoT devices.
MIPI SLIMbus is designed primarily for transporting audio between larger components. Figure 8 illustrates examples such as modems and application processors interfacing with peripherals such as Bluetooth, FM and audio subsystems/codecs.
SLIMbus v2.0 is a two-wire, multi-drop, TDM interface that supports multi-master and multiple devices. It employs CMOS I/O running in single data rate (SDR) up to 28MHz, with fixed frame size, support master and clock hand-over capabilities for low-power operation. SLIMbus v2.0 also supports multiple multi-channel, high-quality audio streams, phase coherence to enable stereophonic sound, microphone arrays and other compelling features. It also supports scalable bandwidth up to eight lanes per device for a peak aggregated bandwidth of up to 224Mbps.
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MIPI SoundWire is a complementary specification to MIPI SLIMbus. Introduced in 2014, SoundWire consolidates the key attributes in mobile and PC industry audio interfaces and provides a common, scalable architecture that can be used to enable comprehensive audio features in multiple types of devices across market segments.
MIPI SoundWire is a unified interface designed primarily for small audio peripherals. It is optimized for low-complexity, low-gate-count designs to support the use of cost-sensitive audio components such as digital microphones, digital speakers and advanced amplifiers in mobile handsets. In addition, it can optimize speaker protection, microphone power and performance, noise cancellation and “always-listening” audio input.
SoundWire shares many SLIMbus features. SoundWire v1.1 also employs CMOS I/O and supports up to 11 slave devices, multi-channel audio, PDM format and in-band control/interrupts/wake. However, it runs in double data rate (DDR) mode up to 12.288MHz (up to 24.576 Mbps), and supports configurable frame size and enhanced low latency protocol. Optional multi-lane extensions up to eight data lanes are available to support high-end audio applications. For example, eight-channel 192 KHz 24-bit audio requires 8 * 24 * 192000 = 36.864 Mbps, which would require two or more lanes, while it may operate at a lower frequency to optimize for power accordingly.
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Figure 9 shows an example of an application processor directly connecting to multiple digital microphones and speakers over SoundWire. This is a typical use case.
MIPI SoundWire and MIPI SLIMBus can operate collaboratively in a system through bridging solutions, enabling a flexible yet sophisticated audio system for mobile or mobile-influenced platforms. Figure 10 shows an example.
MIPI SLIMbus and SoundWire are ready to support the first generation of 5G smartphones. SLIMbus is a mature specification with mature audio components, and deployed in advanced smartphones and mobile-influenced platforms. SoundWire is rapidly gaining momentum as an enabler for digital microphones and speakers in high-end smartphone platforms. Both SLIMbus and SoundWire are expected to be deployed in the first wave of 5G smartphones that come to market between late 2018 and late 2019.
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3.1.2 MIPI CSI-2: 4K and 8K Video with High Frame Rates and High Color Depth
MIPI CSI-2 is the primary camera interface in virtually all 4G LTE smartphones and is already being used in the first wave of 5G smartphones. MIPI CSI-2 specifications support flexible mobile design with multi-cameras, depth/time-of-flight (ToF) and face-detection sensors. Today’s high-end and mainstream 4G smartphones support up to two rear-facing sensors, and a few models have three. Tomorrow’s 5G devices will have two-sensor with Tele+Wide, Color+Mono, Main+Depth sensors, or the aforementioned two-sensor + Eye / Face detection / ToF sensor in three-camera configurations. All of these implementations can be supported by MIPI CSI-2 coupled with MIPI D-PHY or C-PHY physical layers.
CSI-2 v2.1 over C-PHY v1.2 delivers up to 8.0 Gbps (3.5 Giga symbols per second, or Gsps) with embedded clock and data over three wires per lane, and supports lane expansion (up to 24 Gbps with three C-PHY lanes using nine wires). CSI-2 also supports D-PHY v2.1 delivering up to 4.5 Gbps with forwarded clock and data over four wires and supports data lane expansion (up to 18 Gbps using 10 wires).
The main camera in 4G smartphones is currently 12-16MP, with some models as high as 40MP. With 4K/30fps video capture now common, 4K/120fps and 8K/30fps video capture are likely to become available around 2021. CSI-2 v2.1 can already support these high resolutions and frame rate combinations, even with high-color depth RAW20 (8K x 30fps x 20 bit/RAW pixel = 20 Gbps). They also are well within the capabilities of the next-generation CSI-2 and C-PHY/D-PHY data rates.
But CSI-2 is more than simply resolution, frame rate and bandwidth. The MIPI Camera Working Group continues to drive advanced features to enhance emerging 5G use cases such as AI/machine vision, AR/VR and connected vehicles. These advanced features include:
- Latency reduction transport efficiency (LRTE) to reduce transport latency, facilitate real-time perception, processing and decision-making; and optimize transport efficiency to reduce the number of wires, toggle rate and power.
- Eye tracking (AVRET), camera-to-camera sync, camera-display sync for AV/VR applications.
- Smart regions of interest (SRoI) to enable distributed- and hybrid-vision architectures.
- USL (Unified Serial Link) to help facilitate native long-reach support for IoT product platforms.
- RAW 12-10-12 compression/decompression reduces bandwidth while delivering superior signal-to-noise ratio (SNR) images devoid of compression artifacts for mission-critical vision applications.
- RAW-16, RAW-20 and RAW-24 color depth for superior image quality that vastly improves intra-scene high dynamic range (HDR) and SNR for high quality imaging and can bring “advanced vision” capabilities to autonomous vehicles and AI systems.
- Enhanced CCI (Camera Control Interface) and CCS (Camera Command Set) supporting I2C FM+ and MIPI I3C SDR and HDR_DDR modes for higher throughput, lower latency camera control.
- Scrambling and SSC (spread spectrum clocking—MIPI D-PHY only) to reduce power spectral density (PSD) emissions and minimize radio interference.
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Beyond Smartphones: Drones, IoT, Automotive and More
MIPI CSI-2 supports a wide array of low-cost and high-quality image sensors at different resolutions, frame rates, quality and color depths. This combination of selection and capabilities makes it a popular choice for what’s sometimes referred to as “mobile++” devices. Examples include AR/VR headsets, drones (Figure 11) and IoT endpoints.
Automotive OEMs and their suppliers frequently use MIPI CSI-2 for applications that require unified end-to-end imaging and near-real-time processing and decision making (Figure 12). The MIPI Camera Working Group is currently planning an optimized MIPI camera solution to support the stringent automotive environment and certain IoT use cases:
- Native support for a long-reach channel mapped to automotive or IoT platforms, (e.g., drones).
- Unified Serial Link (USL) with guaranteed transport for mission critical (e.g., autonomous vehicle) applications
- Synchronizing image sensors for advanced vision applications
- Provision for end-to-end security (e.g., Interleaved AES-256)
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The MIPI CSI-2 specification is the interface of choice for 4G applications ranging from smartphones to drones to connected vehicles. This preference is continuing into 5G, where CSI-2 is already enabling the first wave of 5G devices, starting with smartphones. The CSI-2 specification for the 2021 market will contain the state-of-art bandwidth/resolution and features, with support for multi-camera, depth sensing, LRTE, USL, AVRET, SRoI, RAW-16/-20/-24, Enhanced CCI with I2C_FM+ and I3C support. All of these features will substantially enhance mobile user experiences with 5G mobile devices.
3.1.3 MIPI DSI-2: 4K and Beyond Displays for Smartphones and AR/VR Headsets
Smartphone display resolution and pixels per inch (PPI) have continually increased over the years, a trend that will continue for the foreseeable future. This trend increases display bandwidth and power consumption. As Figure 13 illustrates, display payload bandwidth has increased at a rate of 8-10 times every five years.
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To address this trend, the MIPI Display Working Group collaborated with VESA’s Display Stream Compression (DSC) Task Group. MIPI DSI v1.2 adopted the VESA DSC standard in 2014 to provide up to 4:1, 8 bpp visually lossless compression. MIPI Alliance and VESA have continued their collaboration. For example, in May 2018, DSI-2 v1.1 adopted the latest VESA VDC-M standard, which delivers up to 5:1, 6 bpp visually lossless compression. DSI-2 v1.1 over MIPI C-PHY v1.2 delivers up to 8.0 Gbps (3.5 Gsps) with embedded clock and data over three wires per lane, and supports lane expansion (up to 24 Gbps with three C-PHY lanes using nine wires). This is equivalent to 8.0 Gbps x 3 C-PHY lanes x 5 = 120 Gbps effective bandwidth per DSI link with 3 C-PHY v1.2 lanes. DSI-2 v1.1 also supports D-PHY v2.1 delivering up to 4.5 Gbps with forwarded clock and data over four wires and supports data lane expansion (up to 18 Gbps using 10 wires).
Smartphone display resolutions are not expected to exceed 4K or 5K resolution (800 and 1000 PPI at 5.5” screen size, respectively), while tablet and laptop resolutions are not expected to exceed 8K or 10K resolution (572 and 715 PPI at up to 15.4” screen size, respectively) even beyond 2021. The main reasons are that it is both technically difficult to achieve this high resolution, and it would have limited or no visual quality improvement at such high PPI, according to many studies. These resolutions and bandwidths are already supported by DSI-2 v1.1, which meets and exceeds the state-of-the-art requirements beyond 2021. At the same time, DSI-2 also effectively reduces the physical bandwidth while enabling device designs that cost less, are smaller due to fewer wires and have longer battery lives.
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MIPI DSI-2 is also the de facto choice in many AR/VR display devices, such as head-mounted displays (HMDs) and glasses. 5G will enable better and richer AR/VR user experiences, which will require better HMD displays. Researchers are working to reduce so-called “VR sickness,” potentially by adding some form of head- and/ or eye-tracking sensors, display and audio synchronization and other tricks to avoid sensory conflicts to the human brain. MIPI specifications are ready today to enable these features, illustrated in Figure 14, that help address VR sickness.
The MIPI Display Working Group will continue to investigate the implications of 5G and potential enhancements, such as a high-bandwidth, low-latency return channel to support and enrich emerging 5G use cases.
MIPI DSI-2 currently is the world’s most widely used interface for 4G smartphones and other devices with displays that have ever-higher resolution and PPI requirements. The MIPI Display Working Group continues to enhance DSI-2’s capabilities to meet emerging market requirements, such as by collaborating with VESA’s Display Stream Compression (DSC) Task Group to provide up to 5:1, 6 bpp visually lossless compression. These and other initiatives also ensure that DSI- 2 is ideally suited to enable 5G smartphones, AR/VR HMDs and other devices with more advanced requirements.
3.1.4 MIPI D-/C-/M-/A-PHY: High-Bandwidth, Power-Efficient Physical Layer Connections for Various Application Layers
MIPI offers a family of three high-performance and cost-optimized physical layer specifications: D-PHYSM, M-PHY and C-PHYSM. MIPI D-PHY is already the predominant PHY layer deployed today, coupling with CSI- 2 and DSI-2 in virtually all 4G LTE smartphones. Meanwhile, M-PHY paired with MIPI UniPro/JEDEC UFS are the high-performance mobile storage interfaces of choice in today’s LTE devices and in the first wave of 5G smartphones. With the latest MIPI CSI-2 and DSI-2 specifications and industry support, it is expected that C-PHY adoption will ramp up quickly as well.
MIPI D-PHY is the most widely deployed low power physical layer in the mobile industry. Optimized for MIPI CSI-2 camera and DSI/DSI-2 display protocols, D-PHY delivers high performance, low power and low EMI, making it compatible with sophisticated RF subsystems in mobile devices. D-PHY v2.1 supports up to 4.5 Gbps/lane and supports data lane expansion up to an aggregated data rate of 18 Gbps using 10 wires utilizing 4 data lanes plus one clock lane.
MIPI C-PHY provides high-throughput performance over bandwidth-limited channels to connect displays and cameras to an application processor. C-PHY accomplishes this by departing from the conventional differential signaling technique on a two-wire lane by use of a three-phase symbol encoding achieving ~2.28 bits/symbol over a three-wire lane. Each lane includes an embedded clock. C-PHY v1.2 supports up to 3.5 Gsps/lane with an equivalent of 8 Gbps/lane, and can achieve a peak bandwidth of 24 Gbps over three lanes.
MIPI M-PHY is a performance-driven and versatile physical layer targeting multimedia, high performance storage and chip-to-chip interconnect use cases. It uses a differential signaling with an embedded clock, supports two transmission modes with different bit signaling and clocking schemes, as well as multiple high-speed gears, offering configuration choices for run-time optimization between performance and power. M-PHY v4.1 supports 11.6 Gbps/lane, with an aggregated bandwidth of 46.4 Gbps over four lanes.
M-PHY is mostly used in combination with the MIPI UniPro protocol, which supports JEDEC’s Universal Flash Storage (UFS). as a reliable, high-performance transport, low-power, and low-latency link. UFS v2.1 is already the predominant mobile storage found in high-performance 4G smartphones and will also be deployed in first-generation 5G smartphones. Meanwhile, UFS v3.0 will continue to enable state-of-the-art mobile storage for the flagship devices in the 5G era by fully utilizing M-PHY v4.1 performance capabilities. MIPI M-PHY is also the PHY of choice for the MIPI CSI-3, MIPI DigRF, MIPI LLI and MIPI UniPro protocols.
The MIPI PHY family of specifications are 5G ready. Refer to Section 3.1.2, 3.1.3 and 3.1.8 to learn more about how current D-PHY v2.1, C-PHY v1.2 and M-PHY v4.1 specifications already exceed the industry’s 2021+ performance and bandwidth requirements.
The MIPI PHY Working Group continues to drive the next-generation PHY specifications to meet 2024+ 5G needs, to suit new 5G use cases and to target “beyond mobile” applications such as IoT and automotive. Upcoming C-PHY v2.0 and D-PHY v3.0 specifications target data rates up to 6 Gsps/lane and 14 Gbps/data lane, respectively. They also aim to support IoT use cases with much longer channels than in mobile form-factor devices, while preserving the benefit of MIPI PHYs to offer a low power, low latency, and low EMI solution. Also a new M-PHY specification is under discussion, which would target a data rate of about 23 Gbps/lane along with latency reductions to become even more power efficient. An increased efficiency may also be achieved through an advanced encoding scheme.
MIPI is also addressing automobile use cases for surround sensor as well as display applications. As MIPI protocols are widely employed by camera sensors and displays, it is desirable, that MIPI also offers a solution for an automobile link, to connect such devices to a central processing unit. With development of the MIPI A-PHYSM physical layer specification already underway to meet 12-24 Gbps, requirements gathering has begun to support higher speeds including over 48 Gbps for display and other use cases. When complete, these specifications will serve a broad spectrum of the automotive industry’s future connectivity needs into the 5G era.
MIPI A-PHY v1.0 is expected to be available to developers in late 2019. The specification will optimize wiring, cost and weight requirements, as high-speed data, control data and optional power share the same physical wiring. The asymmetric nature of the MIPI A-PHY link, its point-to-point topology and its reuse of generations of mobile protocols promise overall lower complexity, power consumption and system costs for developers and automotive OEMs. It’s anticipated that the first vehicles using A-PHY components will be in production in 2024. In addition to automotive uses, the configuration of the specification will be well suited for applications such as IoT and industrial.
MIPI D-PHY, M-PHY and C-PHY are the de facto standards for high-performance, cost-optimized physical layer specifications in 4G device , as well as the first wave of smartphones. They deftly balance the marketplace’s bandwidth, latency and power requirements for applications such as displays and cameras, while providing OEMs with choices. Forthcoming enhancements to MIPI’s existing PHYs and the new MIPI A-PHY will enable generations of MIPI mobile protocols to be adapted to automotive, IoT and other emerging use cases.
3.1.5 MIPI RFFE: Flexible Front Ends to Support Dozens of 5G Bands and MIMO Antennas
The MIPI RFFE specifications are the industry standard and dominant control backbone for RF front-end devices in smartphones.
MIPI RFFE specifies a two-wire, point-to-multipoint (multi-drop) control bus to control a variety of RF front-end devices, as illustrated in Figure 15. Examples include power amplifiers (PAs), low-noise amplifiers (LNAs), filters, switches, power management modules (PMUs, PMICs) and antenna tuners, to mention only a few. The interface also supports 1.8V and 1.2V IO voltage (VIO).
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Since the initial RFFE v1.0 release, in order to meet the demanding and increasingly complex RF front-end subsystems, MIPI has introduced many new features in RFFE v2.0 to support LTE and LTE-A requirements, including:
- A multi-master feature to support MIMO, carrier aggregation and the monitoring of alternate bands.
- An increase of bus frequency from 26 MHz to 52 MHz, doubling the throughput from RFFE v1.x.
- Due to the variety and large number of devices using RFFE, the Extended Product ID was added along with the additional USID programming procedure.
The MIPI RFFE Working Group is actively driving the specification updates and roadmap to meet 5G NR requirements. As Figure 16 summarizes, the latest release, RFFE v2.1, introduced additional features:
- Multiple message types: master context commands and a new masked write command sequence for read-modify-write (RMW) needs.
- Flexible bus configuration: extended manufacturer ID bit field, extended triggers, updated bus load values and additional trace length timing tables for various bus driver implementations.
- Longer reach (or trace lengths) to accommodate buses needing further bus reach in some applications.
- Additional reserved register space for future features.
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RFFE v2.1 is designed to perform well with 5G NR radio FR1 (sub-6 GHz) bands and will see deployment in first-generation 5G smartphones.
The MIPI RFFE Working Group continues to investigate requirements for a next-generation RFFE to support 5G NR FR2 (24.25 GHz to 56 GHz) bands and requirements for 5G NR Phase 2, also known as 3GPP Release 16. Future RFFE specifications plan to address enhancing capabilities such as higher data rates, more Tx/Rx paths, shorter configuration time (target <= 1μS) to meet shorter transient time and more flexible programmability, among others.
The MIPI RFFE specifications are the industry standard and dominant control backbone for a wide variety of RF front-end devices, including PAs, LNAs, filters, switches, PMUs, PMICs and antenna tuners. These specifications are continually enhanced to support emerging use cases and marketplace requirements, such as MIMO, carrier aggregation and the monitoring of alternate bands for LTE-A smartphones. Work has already begun on the development of a next-generation RFFE to support 5G massive MIMO and 5G NR FR2 requirements in millimeter Wave (24.25 GHz to 56 GHz) bands.
3.1.6 MIPI VGI: Consolidating Sideband GPIOs and Low-Speed Messaging Interfaces
The Virtual GPIO Interface (VGI), illustrated in Figure 17, is a MIPI specification under development as of fall 2018. It is focused on consolidating sideband GPIOs and low-speed messaging interfaces (e.g., UART, SPI) over a two- or three-wire full-duplex point-to-point interface to bring packaging and system-level I/O pin reduction while meeting sideband signaling and messaging needs.
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The following key features will be supported in VGI 1.0:
- Bi-directional virtual GPIO state information exchange
- Transmission latency within the permissible limits
- Wide range of clock frequency support (from sleep clock to higher frequency (78 MHz)
- Dynamically switchable clock gears
- Ability to detect physical interface failure under corner case conditions, such as power failure, or a watchdog timer bite that renders the SoC unable to communicate via standard bus-based communication
- Minimal to no software required for driving the interface
- For lower transmission latency, a third wire providing clock is permitted, making it a three-wire VGI interface
- Minimum impact on power and die area
- Two-wire mode default signaling scheme: PWM with data rates up to 4 Mbps
- Two-wire mode alternate signaling scheme: UART-NRZ with data rates up to 4 Mbps
- Three-wire mode synchronous mode signaling scheme: Synchronous mode with clock rate up to 78 MHz
VGI v1.0 will support both 1.2V and 1.8V I/O operations. At 4 Mbps operation, it will be able to support trace or physical wire length of up to 90cm. At 78 MHz operation, the VGI interface length will be limited to 10 cm. Under all interface conditions, no termination will be required.
Some 5G IoT devices will require a large number of I/O pins without compromising real-time performance requirements. These devices could also use VGI as the main interface between the application processor and I/O expander. Thanks to these features, VGI is expected to be an interface of choice between low-speed modems and a host controller in 5G IoT devices.
The Virtual GPIO Interface (VGI) is a MIPI specification under development that will consolidate sideband GPIOs and low-speed messaging interfaces such as UART and SPI over a two- or three-wire full-duplex point-to-point interface. This architecture will enable packaging and system-level I/O pin reduction while meeting sideband signaling and messaging needs. MIPI VGI is designed to support 5G use cases such as low-to-mid-speed IoT applications.
3.1.7 MIPI I3C: Multi-Sensor Support and Ubiquitous, Legacy Low-Speed Interface Convergence
MIPI I3C is a relatively new two-wire interface initially developed for connected sensors, hubs and application processors, as illustrated in Figure 18. It is poised to be deployed in the 5G smart devices coming in 2019.
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MIPI I3C features circuit simplicity, maximum effective data rate of greater than 33Mbps with a 12.5MHz clock, in-band interrupt capability, dynamic address assignment, hot join support, common command codes and timing control while maintaining backward compatibility with I2C and attaining proven industry interoperability. These features put MIPI I3C well on its way to becoming the dominant interface for advanced and highly accurate sensors, and converge previous market fragmentation between I2C, UART, SPI and other legacy low-speed interfaces. These are all welcomed capabilities with respect to 5G readiness.
MIPI I3C is leveraged by other specification efforts inside and outside of MIPI, including CCI for CSI-2 v2.1, MIPI Touch TCS/ALI3C and Debug for I3C specifications. Additionally, the MIPI Sensor Working Group is working to advance I3C further with v1.1, expected in late 2018. New features such as grouped addressing, comprehensive flow control, advanced error handling and multi-lane for speed support promise to ensure I3C continues to be the ubiquitous low-speed interface of choice for connected and smart devices.
The MIPI I3C two-wire interface is ideal for advanced, highly accurate sensors, hubs and application processors in 5G smartphones and other devices. Its key features include circuit simplicity, a maximum effective data rate of greater than 33 Mbps with a 12.5 MHz clock, in-band interrupt capability, dynamic address assignment, hot join support, common command codes and timing control. MIPI I3C v1.1, expected in late 2018, will add features such as grouped addressing, comprehensive flow control, advanced error handling and multi-lane for speed.
3.1.8 MIPI UniPro and M-PHY: Eliminating Memory Access Bottlenecks
MIPI UniPro and M-PHY enable lower energy/bit than other mobile storage interfaces in active mode, while the faster data transfer also shortens the active mode duration and reduces the total system power.
JEDEC’s UFS 2.1 and UFS 3.0, which is based on MIPI UniPro v1.6 coupled with M-PHY v3.1 and UniPro v1.8 with M-PHY v4.1 respectively, deliver unprecedented aggregated transport bandwidth of 11.6 Gbps and 23.2 Gbps per direction, respectively. These enable faster boot, smoother scroll, faster web browsing and switching tabs, faster multimedia and higher gaming performance.
MIPI UniPro is ready for a variety of 5G applications, starting with smartphones. The UFS v2.1 specification is already the predominant mobile storage in standard high-performance 4G LTE smartphones and is expected to drive wider adoption in the mainstream and value segments with its substantial performance and power benefits. At the same time, UFS v3.0 is powering the next generation flagship smartphones in the era of 5G. Figure 19 illustrates this performance evolution.
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It should also be clear that 5G will have no direct implications on mobile storage performance. It is expected that application developers will continue to leverage 5G’s high data rate and low latency to push the limit of eMBB and create 5G use cases that will benefit from faster storage performance. Current UFS v3.0 specifications, with a peak transfer rate of 2.9 GBytes per second, would have enough headroom for flash device manufacturers to build high-performance UFS chips or cards to fuel future advanced 5G use cases.
Nevertheless, with the increasingly complex 5G platform, the size of firmware, OS and applications are expected to increase and will take longer time to load. The MIPI UniPro Working Group will continue to evaluate how to further enhance the performance and capabilities to enable the next generation of 5G platforms.
MIPI UniPro and M-PHY are designed to meet marketplace requirements for storage access that’s both fast and power-efficient. MIPI UniPro supports a variety of 5G applications, starting with smartphones. The UFS v2.1 and v3.0 specifications are the de facto standard for high-performance 4G LTE smartphones and ideally suited to support their 5G counterparts.
3.1.9 MIPI Debug: Tools for Ensuring Robust Performance
The MIPI Debug family of specifications enables a debug framework and architecture for the SoCs used on 5G-enabled platforms. These specifications include debug subsystems for access and control, instrumentation and visibility, and different physical and network interfaces. The MIPI Debug family of specifications focuses on:
- Minimizing the pin cost and increasing the performance of the basic debug interface for mobile devices.
- Deploying debug connectors that are physically robust and have the performance required for the high bandwidth demands of 5G devices.
- Developing generic trace protocols that allow many different on chip trace sources and 5G applications to share a single trace data flow to the debug tools.
- Maximizing debug visibility in fielded systems by reusing some of the functional interfaces and/or connectors for debug.
- Utilizing the high bandwidth functional interfaces being deployed on 5G systems as a transport for debug.
More information about how the MIPI Debug family of specifications can be used to enable a debug solution can be found in the MIPI Architecture Overview for Debug white paper.
Table 2 provides an overview of how MIPI specifications are ready for use today in 5G devices such as smartphones.