Status: Hibernated


The MIPI Low Latency Interface (MIPI LLI) Working Group, formed in 2010, is chartered to specify point-to-point interconnections between two dies, wherever the dies are located in a full system. Among other properties, interfaces developed by the group are intended to support address-based transactions between on-chip interconnects; use a packet-based mechanism to transport information; and employ MIPI M-PHY in a dual-simplex configuration at the physical layer.

Industry Need

The MIPI LLI Working Group responds to the manufacturing community’s need to optimize use of board space; reduce pin count, power consumption and costs; and shorten design cycles to expedite time to market with new designs. 


The group focuses on interconnecting the application processor and the modem/baseband processor in a manner that allows the two chips to share memory for data and programming.  The approach also enables remote configuration and memory mapped transfers as if the two chips are a single chip and memory mapped I/Os. 


The current specification resulting from the group’s work, the MIPI Low Latency Interface v2.1 (released November 2014), enables designers to eliminate a dedicated memory chip. It provides additional practical benefits. For example, it allows the use of sideband signals between the application processor and baseband processor to further improve system communication.

The group requested to be placed in hibernation status for 2017 and can reactivate when new projects or specification development is needed.

About the Group: 


Vice Chair
Abdelaziz Goulahsen, STMicroelectronics

MIPI Alliance members at the Contributor level and above may participate by subscribing to the group on the member website.