Accelerating System Level Verification of SOC Designs with MIPI Interfaces (Cadence)
Abstract: MIPI CSI-2 (Camera Serial Interface) and MIPI DSI (Display Serial Interface) specifications are well adopted, and are integrated in many mobile and automotive complex systems. Pre-silicon verification of those systems is challenging, time consuming, and requires significant effort and resources. Prototyping and Emulation are common methods to shorten and enhance this effort. This paper will focus on Acceleration for system level verification, for benefiting from both simulation and emulation advantages. Acceleration enables emulating the design and accelerating its run time, while using a SW/HW bridge to enable a simulator interface to drive interesting scenarios in a flexible and robust way. Enables validation and early development of software on hardware. Showcase a real time demonstration platform for driving images via a CSI-2 and display real time on DSI using Virtual Models.
Arindam Guha has extensive experience in leading hands on technical pre-sales efforts and proliferation of simulation/hardware-accelerated functional Verification IP's for industry standard protocols (spanning across simulation to acceleration). Arindam is proficient in standard mobile/storage and communication protocols like PCIe, USB, AMBA family, OCP, MIPI family, Display Port, Ethernet, SAS/SATA, JTAG, Standard Memories (DDR family, UFS etc.). Arindam has hands-on experience in architecting test benches using UVM, OVM and VMM methodologies.
Yafit Snir is currently responsible for the development of MIPI Verification IPs aimed for emulation at Cadence. Yafit has over 14 years of experience in hardware verification and software development and holds a B.Sc. in electrical engineering and computer science from Tel Aviv University. Yafit is a M.Sc. candidate in electrical engineering, specializing in Evolutionary algorithms. (Publication: “Tailoring ε-MOEA to Concept-Based Problems”, Springer)"