IO Aggregation/De-Aggregation in Mobile and Mobile Influenced Systems to Improve Routing Congestion (Lattice)
Abstract: Over the years, a large variety of low-speed I/O interfaces have proliferated in various systems in order to provide critical functionality such as: system configuration, power management, system resets, debug, firmware updates & other low-speed data communications. For example, consider the highest volume mobile system (Ref: MIPI System Diagram) there are about a dozen low-speed interfaces. Typically, these interfaces include multiple instances I2C, SPI, UART, SPMI and 1-wire. As the bandwidth requirement is small, these wires carry disproportionately higher cost per bandwidth compared to higher speed interfaces, say, based on D-PHY and PCI-Express. As the mobile components are being adopted in emerging mobile-influenced applications like drones, AR/VR, and automotive, these slow-speed interfaces tend to add non-trivial system cost, especially, if these have to be extended over longer distances and/or through connectors or hinges. In this presentation, we will address how to aggregate multiple slower-speed interfaces over one or two wires by using ultra-low power and small size mobile FPGAs. We will show that one or two wires running at speeds up to 100Mbps can carry the traffic associated with many of these interfaces as well as various GPIOs. We will discuss the tradeoffs involved among multiple requirements which include bandwidth, latency, number and types of interfaces, SW drivers and platform support.
Ying Chen is the Senior Business Development Manager at Lattice Semiconductor focusing on emerging consumer applications such as VR/AR, drones and IoT. Chen has 20 years of experience in the high tech industry and prior to Lattice, he managed sales in China and Taiwan for Altera in various market segments. Chen received his bachelor’s degrees in Electrical Engineering and Computer Science (EECS) and Materials Sciences & Engineering from University of California, Berkeley.