Wednesday, September 15, 2021

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Overview 

This webinar covers recent updates to the MIPI I3C®, I3C Basic℠ and I3C HCI℠ specifications, and explains how the unique power-saving features of MIPI I3C can enable ultra-low-power designs.

 

Who should attend

Design engineers, test engineers, post silicon validation engineers, system design engineers, engineering managers, application engineers, SoC emulation engineers, RTL engineers, firmware engineers and hardware engineers, etc.

 

Agenda

The MIPI I3C/I3C Basic specifications provide a scalable, medium-speed, utility and control bus interface for connecting peripherals to application processors, streamlining integration and improving cost efficiencies. As the successor to the legacy I2C interface, I3C gives developers new capabilities to craft innovative designs for a broad array of products—from smartphones, to wearables, to systems in automobiles and server environments. 

MIPI Alliance recently released the first update to its publicly available MIPI I3C Basic specification (v1.1.1), as well as additional updates to the core I3C specification (v1.1.1) and its I3C Host Controller Interface specification (v1.1). An I3C HCI Linux driver was also implemented in the 5.11 kernel late last year. 

The first half of this webinar will provide a brief introduction to the three specifications, along with an overview of what’s new in each, with particular focus on I3C Basic v1.1.1, which contains a number of key enhancements since its original introduction. 

The second part of the webinar will cover the more practical aspects of the I3C specifications, highlighting key power-saving features (not supported by I2C or SPI) that can enable highly power-efficient designs that satisfy ultra-low-power use cases. The presentation will include a comparison of I3C’s power efficiency against legacy interfaces, and example use cases to demonstrate the use of “hot join” to power up and down a system, and “routing devices” to enable the coexistence of high and low activity I3C buses.

After the presentation(s) there will be a live Q&A session with the speakers.

 

Presenters

Tim McKee, 2021 MIPI webinar presenter

Tim McKee
Tim McKee, a system architect from Intel Corporation, works to create and enable standards for industry advancement. Over the last year, Tim has worked as the MIPI I3C Working Group chair to drive I3C technology forward through the development of MIPI I3C v1.1.1 and MIPI I3C Basic v1.1.1 documents (specifications, FAQ, App Notes, CTS, etc.). Tim also helped lead the liaison activities with I3C/JEDEC to create the JESD403 Sideband Bus specification. Tim has already taken a leadership role with multiple I3C projects including the development of a new specification framework and MCTP over I3C subgroup and is well-equipped to continue his leadership role.

Since the beginning of his career, Tim has worked with many standards bodies, including USB-IF, PCI-SIG, CXL Consortium and of course MIPI Alliance. Through his work, he has held multiple positions, including USB Power Delivery Compliance chairman, and various vice chair and contributor positions. These positions have not only provided great experience, but they also have positioned him to be able to expand I3C into new areas moving forward. Tim holds a bachelor of science degree in electrical and computer engineering from Oregon State University.

Matthew Schnoor, 2021 MIPI webinar presenter

Matthew Schnoor
Matthew is a debug architect at Intel and member of the MIPI Debug Working Group. Matthew has more than two decades of experience in various Intel business groups, primarily focused on software development, silicon validation and system debug architecture. He has enabled MIPI I3C to support MIPI Debug for I3C, and currently works across and within several MIPI working groups to help develop MIPI specifications in support of that goal.

Michele Scarlatella, 2021 MIPI webinar presenter

Michele Scarlatella
As a long-time contributor to the MIPI I3C specification, Michele currently serves as an I3C technical consultant for MIPI Alliance. Formerly, he spent 18 years at STMicroelectronics covering multiple senior roles including director of technology and system architecture within the Microcontroller & ICs division, and director within the central marketing team for secure microcontrollers. He also participated on the board of directors for the Trusted Connectivity Alliance (formerly SIMAlliance) for more than 10 years. Michele began his career in basic scientific research and academia, working at the Stanford Linear Accelerator Center. He holds three patents and has published more than 50 scientific papers.