Tuesday, May 10, 2016

Presented on:
10 May 2016

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Overview

As mobile and mobile-influenced systems continue to include a greater level of functionality, the number of sideband GPIOs in such systems continues to increase. Sometimes this number is even more than the number of I/Os needed for the main data link. To minimize the cost and space associated with these GPIOs, MIPI Alliance is working on a Finite State Machine (FSM) centric GPIO-state serialization and deserialization standard, called Virtual GPIO Interface or VGI.   

The transmitting side of the VGI FSM directly connects to the GPIOs and serializes their states to be sent over a bidirectional two-wire data interface or three-wire interface with clock. The receiving side of the VGI FSM de-serializes the incoming GPIO states and assigns them to designated GPIO locations. The VGI interface also includes a messaging aspect, whereby GPIOs, messages, or both can be sent in the serial data stream. In one mode of operation, the data stream resembles the venerable UART signaling protocol, and we may refer to this mode of operation as VGI_UART. The VGI_UART can be configured to be compatible with the existing UART protocol or the extended version of the UART defined by VGI. Following a state machine based approach, VGI can be used in with number of interface scenarios such as  I3C.

This webinar covers this up-coming standard to outline its architecture and system level benefits in numerous applications.

Speaker Bios

Lalan Mishra, Qualcomm Technologies, Inc.

With over 23 years of design and innovation experience in the field of Wireless Embedded Systems (Smartphones/Tablets/eBook etc.), Lalan is currently employed with Qualcomm Inc. as  Sr. Staff Engineer - Advanced Connectivity and Multi-Radio Architecture. In his current role, Lalan focuses  on conceiving next-generation chipset connectivity architecture involving digital and RF circuits with the goal to minimize cost, power, latency and pin-count. Lalan conceived the idea of Virtual GPIO Interface (VGI) back in 2012 and this concept is now in the standardization process at MIPI under the umbrella of Reduced Input-Output Work-Group (RIO-WG), chaired by him.

A proven innovator, Lalan has over 45 active inventions to his credit. He holds a Master’s degree from UCSD with specialization in Wireless Embedded Systems. In his spare time, he loves to dive into Natural Philosophy and plays classical ragas on Indian bamboo flute.

Satwant Singh, Lattice Semiconductor
Satwant has many years of experience in semiconductor chip design and architecture, specially, the IO architecture as it relates to the Field Programmable Gate Arrays (FPGAs). The FPGAs IO architecture has been arguably among the most complex ones compared to pretty much all other types of semiconductor chips, as typically, the FPGAs are expected to interface to not only the advanced/emerging chips, but also many of the legacy ones. Recently, the system cost and complexity associated with low-speed I/Os (often called the GPIOs) have become noticeable compared to the high-speed SERDES based interfaces, like PCIe, HDMI and DP etc. This is the key issue addressed by the RIO (Reduced IO) Work Group within MIPI that is working on a new VGI (Virtual GPIO Interface) specification. Satwant is the Vice Chair of MIPI RIO WG.

At Lattice, Satwant is a Senior Director of Strategic Planning, where he is responsible for ecosystem involvement for the latest developments, as well as, company’s product and capabilities roadmaps, including new product planning. Satwant holds an MSEE from University of Toronto and has over 30 patents. He has a keen interest in the semiconductor chip architectures for the emerging markets including mobile, handheld, wearables, Internet of Things (IOT), as well as, mobile heterogeneous computing etc.

John Oakley, Intel Corporation
John Oakley, an RF Control Architect at Intel Corporation, has over 20 years of successful digital design experience at Motorola, Freescale, Fujitsu, and of course, Intel. His willingness to help and mentor, in addition to his deep technical expertise, make him a key member of Intel’s technical team. John has 11 issued patents and has developed more than 55 successful integrated devices, several of which have shipped in high volumes. He has worked in numerous digital system spaces, and is presently in the transceiver and modem fields focusing on the control planes of cellular platforms. An expert in 3GPP standards and their application to real world devices, John is currently Vice Chairman of the MIPI Working Group RFFE and a member of the MIPI Working groups RIO and TSG.

Beyond the work environment, John is a Ruby Life Master at Bridge and is been a Cub Scout leader.