Status: Active

Charter

The MIPI Reduced Input Output (RIO) working group, formed in 2014, is chartered to develop and maintain specification(s) that reduce the number of I/O pins needed to interconnect a host processor with a peripheral device. The group works to accomplish this with specifications that require little or no software intervention. The RIO working group intersects with other MIPI Alliance working groups to identify interface challenges and collaboratively develop effective solutions.

Industry Need

The MIPI RIO Working Group addresses a variety of fundamental I/O proliferation problems. For example, mobile terminals typically use numerous general purpose I/Os (GPIOs) to provide low speed sideband signaling between components, yet the approach requires high numbers of pins and PCB traces, which drives up costs.  Designers have been able to use I/O expanders to augment the available GPIOs, but this approach requires extra board space, increases power requirements and drives up costs. Furthermore, the industry has not had an I/O reduction solution that supports configurations without or minimal software driver changes — a drawback that adds complexity and cost.

Focus

The group has focused its first efforts on maximizing communications capability via sideband signals while minimizing the number of I/O pins required. This has involved developing a virtual GPIO interface architecture that minimizes hardware complexity and software overhead. 

Accomplishments

The MIPI RIO Working Group has developed the MIPI Virtual GPIO Interface (MIPI VGI), which virtually enables sideband signaling between components to reduce the overall number of I/O pins, allowing package size and PCB area reduction. MIPI VGI can be used with MIPI and non-MIPI protocols, and allows easy integration with other serial interfaces, such as UART, I2C and the sensor interface, MIPI I3C.

The group is actively working to develop additional approaches that help reduce the number of I/Os in a device.

About the Group: 

Chair
Lalan Mishra, Qualcomm Technologies, Inc.

Vice Chair
Satwant Singh, Lattice Semiconductor  

Participation
MIPI Alliance members at the Contributor level and above may participate by subscribing to the group on the member website.