A compliant I3C Device that can fulfill the Controller Role is required to:

  • Assign a unique Dynamic Address to any I3C Targets on the I3C Bus, using any combination of the ENTDAA, SETDASA, and SETAASA CCCs that is appropriate for such I3C Targets.
    • Specification Section 5.1.4.2 defines the full requirements of the Dynamic Address Assignment procedure.
    • The specific CCCs and known Static Addresses (if any) must be a prior configuration, i.e., already known to the system designer.
    • Note that the SETAASA CCC was not defined in MIPI I3C v1.0, it was added in v1.1.
  • Manage its Pull-Up structures, including the Open Drain class Pull-Up and High-Keeper Pull-Up for both SDA and SCL. Specification Section 5.1.3.1 defines the full requirements for these Pull-Up structures; see also Q21.3 ("When is the Pull-Up resistor enabled?") and Q21.4 ("Is a High-Keeper needed for the I3C Bus?").
  • Manage START requests and Address Header arbitration in Open Drain mode.
  • Recover I3C Target Devices using the Error Recovery Escalation Model (per Section 5.1.10).
  • Support all of the CCC commands that are mandatory for Controllers, including ENEC, DISEC, ENTDAA, SETDASA, RSTDAA, GETCAPS, RSTACT, GETPID, GETBCR, GETDCR, and GETSTATUS.

Note: The requirements above apply to the I3C Device that is the Primary Controller of its I3C Bus (i.e., the first Active Controller). An I3C Device that is a Secondary Controller during Bus initialization (or one that subsequently joins after Bus initialization) does not need to meet all of these requirements. See specification Section 5.1.7 for specific requirements for I3C Buses with multiple Controller-capable Devices, including reduced-function Secondary Controllers.

FAQ Type: 
I3C