In addition to the Multi-Lane changes for HDR-BT Mode (see Q18.17, "What has changed with the MLANE CCC and Multi-Lane Device configuration?"), specification Section 5.2.4 now adds:

  • Definitions on how to compute the Parity bits in the HDR-BT Header Block
  • Definitions and examples for the CRC-16 and CRC-32 polynomials as used for HDR-BT CRC Block checksums
  • Clarifications on how the HDR-BT CRC checksum values are calculated based on the data for each HDR-BT transfer
  • Correction of an error in the figure showing Direct CCC flows in HDR-BT Mode
  • Clarifications on the use of Group Addresses for Direct CCC Read/Write segments in HDR-BT Mode
  • Correction of a specification error concerning the use of HDR-BT CRC Blocks in CCC Flows in HDR-BT Mode
  • Clarifications to the Transition_Verify byte in the HDR-BT CRC Block; Bits[4:2] are now redefined as always zero
  • Added new figures in specification Section showing the Single-Lane format for all HDR BT Mode structured protocol elements
  • Corrections to the Dual-Lane and Quad-Lane figures for the HDR-BT Mode structured protocol elements, to resolve inconsistencies with the normative text and to show proper SDA Lane bit packing (i.e., the Transition, Transition_Control and Transition_Verify bytes)
  • Detailed explanation of the Data Block Delay mechanism (formerly called the Stall [delay] mechanism), which allows an I3C Target to delay sending the next HDR-BT Data Block until it has collected enough data bytes (see Q19.9, "What is the HDR-BT Data Block Delay mechanism?")
  • Better explanations of HDR-BT flow control details, including a new Section with example HDR-BT transfers with different actions at the flow control points (i.e., the various Transition bytes)
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