An I3C Target may optionally choose to time out if it detects more than 100 µs without an SCL edge (see specification Section 18.104.22.168). If that happens, the Target can abandon the Read and release SDA to avoid a Bus hang when the Controller restarts.
The optional timeout of 100 µs with no SCL activity is a recommended minimum. It does not have to be precise, but since I3C’s minimum frequency is 10 KHz, anything longer than 100 µs means that the Controller has failed to complete the Read, so the Target should High-Z the SDA line and abandon the Read.
Note: If the Target is in Legacy I2C mode, then it would not normally abandon the read, since there is no minimum frequency, and because 9 clocks by a Controller will be enough to abort the Read (since the 9th bit of data is ACK/NACK for a Read in Legacy I2C Mode).