I3C Targets that comply with I3C v1.1+ or I3C v1.1.1 must support the Target Reset Pattern, and at least the Peripheral Reset action (i.e., RSTACT CCC with Defining Byte 0x01).

Although MIPI Alliance strongly recommends true support of Target Reset, such that a Controller can fully reset a Target chip when needed, it is not required. Full/Chip Reset (see specification Section allows replacement of a dedicated pin that would normally be used to reset a Device.

Note: If supported, a Full/Chip Reset causes a typical I3C Target to return to its power-on configuration, which means re-enabling its I2C Spike Filter if it has one. If so, then the I3C Controller must tell the I3C Target to turn off its Spike Filter again (see Q24.1, "Are there any special timing requirements for sending the first START with the Broadcast Address?").

The minimal reset is a reset of the I3C peripheral, at least to a level that will allow a ‘stuck’ I3C peripheral to start working again. How much of a reset that requires is up to the Target vendor; for example, it could be handled by an internal interrupt which would allow firmware/software in the Target to handle the reset.

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