Yes. The I3C Controller must emit the first START with the Broadcast Address (7’h7E) at Open-Drain speeds(i.e., usually I2C Fm+ timings) so that I3C Targets with I2C Spike Filters (per Q15.4, "How does an I3C Target behave with an I2C Controller vs. with an I3C Controller?") will be able to see the I3C Broadcast Address, and then as a result turn off the Spike Filter (per the specification at Section 5.1.2.1.1).

Note:

If another I3C Target arbitrates its own Address (or the special reserved address for a Hot-Join Request) into this Address Header and thereby wins arbitration, then the I3C Controller must repeat this special Address Header.

If such an I3C Target supports Full/Chip Reset using the Target Reset Pattern (which might be preceded by the RSTACT CCC; see specification Section 5.1.11.4), then it will most likely re-enable its I2C Spike Filter after such a Full/Chip Reset. In this case, the I3C Controller must emit the START condition with the Broadcast Address (7’h7E) at Open-Drain speeds again, so that the I3C Target can turn off the Spike Filter.

However, if the Controller knows that none of the I3C Targets has a Spike Filter, then it may omit this. Similarly, if the Controller knows that all of the I3C Targets have accurate Spike Filters, then it may use the I3C 2.5 MHz Open-Drain speed (i.e., 200 ns Low, 200 ns High).

FAQ Category:

FAQ Type: 
I3C