Can reduce the number of I/O pins on components — a group of up to 32 I/O pins could be replaced by one instance of VGI needing 2 or 3 I/O pins
- High performance
- Low power
- Low EMI
- CMOS I/O
- <100 MHz
- 1 – 1.8 Volts
Sideband GPIO virtualization
Consolidation of messaging with GPIO
Elimination of bit-banged GPIOs between processor and peripheral
The MIPI Virtual GPIO Interface (MIPI VGISM) virtually enables sideband signaling between peripherals and the application processor in a device. It can also be used to connect the processor to general peripherals such as hubs, other companion chips or I/O expanders, or to interface devices to a docking station. The interface can significantly reduce the number of I/O pins on components, making it much easier to add components in smartphones, tablets and other mobile-connected devices. For instance, between a host and directly connected peripheral, up to 32 GPIOs could be replaced by a two- or three-wire VGI interface.
In addition to reducing pin count, VGI reduces silicon packaging, board, connector and cable costs. It also improves throughput, maximizes communications capability and reduces power requirements. The architecture can be used with MIPI and non-MIPI protocols. It allows easy integration with other serial interfaces, such as UART, I2C and MIPI I3C.
MIPI VGI accomplishes this by using a finite state machine (FSM) approach to connect GPIOs and serialize their states for transmission over a full duplex two-wire (asynchronous) or three-wire full duplex synchronous interface. The receiving side of the VGI FSM deserializes the incoming GPIO states and assigns them to designated GPIO locations. MIPI VGI combines messaging capability along with sideband consolidation, which also improves efficiency.
MIPI VGI is developed by the MIPI Alliance Reduced Input Output (RIO) Working Group.
Note: Specifications are available only to MIPI Alliance members. For information about joining MIPI, visit Join MIPI.