As embedded audio systems continue to evolve across consumer electronics, automotive and industrial applications, so does the demand to deliver advanced features—such as far-field voice recognition, spatial audio and "always-on" AI-driven audio processing—within increasingly compact, power-sensitive devices such as smart glasses and earbuds, and larger devices such as cars and industrial robots. The recently released MIPI SoundWire I3S (SWI3S™) v1.0 is a new audio interface purpose-built to meet the growing complexity of modern embedded audio systems. The new specification, supporting a link bandwidth of up to 76 Mbps, provides a transformative approach to audio transport by unifying control and data over a single, scalable, low-latency, power-efficient interface.
Legacy audio interfaces like I2S and TDM were not designed to handle the complexity and EMI challenges of today’s systems. These older technologies often require multiple lines for data, control and clocks—leading to increased pin count, board complexity and susceptibility to interference, particularly over long traces or flexible cables.
MIPI SWI3S, developed by the MIPI Audio Working Group, builds upon the proven two-pin, multi-drop architecture of MIPI SoundWire®, introducing greater flexibility and performance. It supports both differential low voltage (DLV) and forwarded bit clock single-ended (FBCSE) PHYs, allowing designers to select the PHY that best meets system requirements, while maintaining a unified protocol and core set of features. SWI3S enables scalable tiered topologies with each link comprising one manager and up to 12 audio peripherals (e.g., microphones, speakers, amplifiers, haptic drivers, hearing aid coils), making it ideal for audio systems of any complexity.
Key features include standardized advanced power management, link-wide multi-channel synchronization, precise audio clock distribution and robust in-band command transport. It also incorporates built-in EMI reduction techniques, such as data scrambling, and offers native test and debug support.
The working group is already working on the next version of SWI3S — v1.1 — which will add support for hub-based and tiered topologies to allow peripherals to act as hubs to extend the SWI3S links to downstream devices. Further, since SWI3S can support multiple PHY types, the hub-based topology will also support mixed-PHY environments.
These features will allow designers to optimize each segment of the audio path based on the physical layout, EMI constraints and power budgets of each audio subsystem, without having to change the high-level transport or control protocols. For even more flexibility, version 1.1 will also add support for a single data rate single-ended PHY, as well as support for running SWI3S protocol over the MIPI SoundWire PHY. These updates are expected to be available in early 2027.
MIPI offers resources and tools for developers interested in the SWI3S specification.