Webinars

MIPI Camera Week - Exploring Imaging System Design Considerations for CSI-2 Over D-PHY and C-PHY

Written by MIPI Alliance | 29 November 2023
 
 

Camera Week Webinars

This webinar explores system architecture implications when using CSI‑2 over D‑PHY and provides:

  • A brief overview of key CSI-2 features, with specific focus on Latency Reduction and Transport Efficiency (LTRE), Scrambling, Unified Serial Link (USL), Differential Pulse Code Modulation (DPCM), and Multi-Pixel Compression (MPC).
  • An exploration of CSI-2 over D-PHY imaging system design considerations, with focus on support for higher channel rates, SoC port/pin optimization and lower RF emissions.
  • Insight into forward-looking imaging system design considerations in conjunction with upcoming D-PHY developments, including the continued introduction of an embedded clock option.
 

This webinar explores system architecture implications when using CSI‑2 over C‑PHY and provides:

  • A brief overview of current CSI-2 features, with specific focus on “Always On Sentinel Conduit” for ultra-low power vision inferencing and “Smart Region Of Interest” to enable smarter image sensors.
  • An exploration of both present- and forward-looking CSI-2 over C-PHY imaging system design considerations, with focus on support for higher channel rates and SoC port/pin optimization.
  • Insight into forward-looking imaging system design considerations in conjunction with upcoming C-PHY developments, including the introduction of a new multi-phase coding scheme. 

Traditionally, Lenovo’s ThinkPad products have contained a USB 2.0 camera with Image Signal Processor (ISP) integrated into the camera module. While this traditional solution provides a low cost and simple system design, the image quality provided by the solution is no longer acceptable to the emerging “hybrid work environment” expectations of today’s customers.

This webinar covers Lenovo's response, to ensure ThinkPad products provide customers with a “best-in-class” video conference experience by utilizing MIPI camera interfaces combined with powerful image signal processing capabilities integrated into a SoC.