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Upcoming Event: MIPI Camera Week - Exploring Imaging System Design Considerations for CSI-2 Over D-PHY and C-PHY
MIPI Alliance
:
17 September 2023

- Resources
- Webinars & Workshops
Camera Week Webinars
27 & 29 November 2023
Register below to join us during the last week of November for a MIPI camera series, featuring two webinars that will explore the system architecture implications of using CSI-2 over D-PHY and C-PHY, and a third that will discuss a member use case focused on how CSI-2 can deliver optimum image quality.
CSI-2 & PHY Webinars
Many embedded imaging system solutions leverage MIPI CSI-2 protocol over MIPI's D-PHY differential physical layer interface or MIPI's C-PHY ternary encoding physical layer interface to connect image sensors to system-on-chips (SoCs). Since the advent of CSI-2 over 15 years ago, these specifications have evolved to include new capabilities to address new use cases within mobile and beyond.
During each webinar, Haran Thanigasalam, MIPI Camera and Imaging Consultant, will be joined by the respective chair of MIPI’s D- and C-PHY working groups, Raj-Kumar Nagpal and George Wiley, to dive deeper into CSI-2 protocol features and PHY-specific imaging system considerations, including forward-looking design considerations based on new capabilities being introduced into the D-PHY and C-PHY roadmaps.
Each webinar will also include an interactive audience question and answer session with the presenters.
An Exploration of MIPI CSI‑2 over D‑PHY Imaging System Design Considerations
27 November 2023 | 8-9 a.m. (PST)
Haran Thanigasalam, MIPI Camera and Imaging Consultant
Raj Kumar Nagpal, MIPI D-PHY Working Group Chair

This webinar will explore system architecture implications when using CSI‑2 over D‑PHY, as well as provide:
- A brief overview of key CSI-2 features, with specific focus on Latency Reduction and Transport Efficiency (LTRE), Scrambling, Unified Serial Link (USL), Differential Pulse Code Modulation (DPCM), and Multi-Pixel Compression (MPC).
- An exploration of CSI-2 over D-PHY imaging system design considerations, with focus on support for higher channel rates, SoC port/pin optimization and lower RF emissions.
- Insight into forward-looking imaging system design considerations in conjunction with upcoming D-PHY developments, including the continued introduction of an embedded clock option.
An Exploration of MIPI CSI-2 over C-PHY Imaging System Design Considerations
29 November 2023 | 8-9 a.m. (PST)
Haran Thanigasalam, MIPI Camera and Imaging Consultant
George Wiley, MIPI C-PHY Working Group Chair

This webinar will explore system architecture implications when using CSI‑2 over C‑PHY, as well as provide:
- A brief overview of current CSI-2 features, with specific focus on “Always On Sentinel Conduit” for ultra-low power vision inferencing and “Smart Region Of Interest” to enable smarter image sensors.
- An exploration of both present- and forward-looking CSI-2 over C-PHY imaging system design considerations, with focus on support for higher channel rates and SoC port/pin optimization.
- Insight into forward-looking imaging system design considerations in conjunction with upcoming C-PHY developments, including the introduction of a new multi-phase coding scheme.
Member Use Case: Camera Image Quality
Delivering the Best Camera Image Quality Using MIPI Interfaces on ThinkPad Notebook
29 November 2023 | 5 p.m. (PST) / 10 a.m. (JST)
Xueyong Yang, Hardware Engineer, System Design Strategy, Lenovo Japan Ltd.

Traditionally, Lenovo’s ThinkPad products have contained a USB 2.0 camera with Image Signal Processor (ISP) integrated into the camera module. While this traditional solution provides a low cost and simple system design, the image quality provided by the solution is no longer acceptable to the emerging “hybrid work environment” expectations of today’s customers.
This webinar will cover Lenovo's response, to ensure ThinkPad products provide customers with a “best-in-class” video conference experience by utilizing MIPI camera interfaces combined with powerful image signal processing capabilities integrated into a SoC.