Quick Facts
- Supports VESA Display Stream Compression (DSC) and VESA Display Compression - M (VDC-M) standards
- Will scale in terms of resolution
MIPI D-PHY and MIPI C-PHY
- High performance
- Low power
- Low EMI
UHD resolution
Embedded displays
Smart meters
Video game devices
Smart watches
Virtual or augmented reality Head-mounted devices
In-sight (glass) devices
Automotive
Industries
Overview
MIPI DSI-2℠, initially published in January 2016, supports ultra-high definition (4K and 8k) required by new and future mobile displays. It specifies the physical link between the chip and display in devices such as smartphones, tablets, AR/VR headsets and connected cars.
MIPI DSI-2 v1.1 incorporates the VESA VDC-M and VESA DSC standards in its transport layer. Companies now have the choice of either codec depending on their bandwidth and power requirements.
For a 30-bit image, VDC-M can enable compression down to 6 bits per pixel providing a compression ratio of up to 5:1, while maintaining visually lossless viewing with no attendant loss of bandwidth.
The combination of VESA’s VDC-M and MIPI DSI-2 and MIPI Display Command Set (MIPI DCS℠) helps systems designers minimize device cost and complexity, maximize battery life and deliver the high-resolution video content that customers seek.
MIPI DSI-2 supports all of the same power-saving features as its predecessor, MIPI DSI®, but adds better resilience to electromagnetic interference by introducing data scrambling.
DSI-2 and PHY Compatibility
Designers can use MIPI DSI-2 on two different physical layers: MIPI D-PHY℠ and MIPI C-PHY℠. The options give designers the flexibility to support different configurations up to four data lanes.
Although the features of MIPI DSI-2 are quite similar to MIPI DSI, the primary difference is its support for C-PHY. However, it also features backward compatibility with DSI on D-PHY. In addition, because MIPI DSI is a mature, stable specification, future developments will be concentrated on expanding the capabilities of MIPI DSI-2.
DSI/DSI-2 PHY Compatibility | |||||
D-PHY 1.01 (1.0Gbps/lane) |
D-PHY 1.1 (1.5Gbps/lane) |
D-PHY 1.2 (2.5Gbps/lane) |
D-PHY 2.0 (4.5Gbps/lane) |
C-PHY | |
DSI 1.0 | Yes | Yes | Yes | Yes | No |
DSI 1.1 | Yes | Yes | Yes | Yes | No |
DSI 1.2 | Yes | Yes | Yes | Yes | No |
DSI 1.3 | Yes | Yes | Yes | Yes | No |
DSI-2 1.0 | Yes | Yes | Yes | Yes | Yes |
DSI-2 1.1 | Yes | Yes | Yes | Yes | Yes |
MIPI DSI-2 is developed by the MIPI Alliance Display Working Group.
Note: The specification is available only to MIPI Alliance members. For information about MIPI Alliance membership, visit Join MIPI.