MIPI Alliance has a family of specifications that can be used to debug components in mobile devices as well as any device that is “smart” or connected, such as an end-point on the Internet of Things. Components that can be debugged with the tools include application processors, modems, device controllers, power management devices, and others.
All of these specifications are available for download and use by the public and the open source community.
MIPI High-Speed Trace Interface (MIPI HTISM) is a serial implementation of the data port, taking advantage of available high-speed serial interface technology used in interfaces such as PCI Express®, DisplayPort™, HDMI® or USB to provide higher transmit bandwidth with fewer I/O pins compared with a parallel implementation. Unlike protocol specifications in the MIPI Gigabit Debug portfolio such as MIPI Gigabit Debug for IPS, HTI is not designed to be used over the high-level protocols implemented by interfaces such as PCI Express, but is intended to reuse the low-level physical high-speed portions of those interfaces in a bare-metal environment.
HTI defines a method to transport a single stream of trace information over a channel consisting of one to eight high-speed serial lanes, using the Aurora 8B/10B protocol (Aurora 8B/10B Protocol Specification, SP002 v2.3). HTI uses the serial simplex mode of Aurora to transmit data in one direction from a target system to a debug test system.
All MIPI debug and trace specifications, including MIPI HTI, are available for download and use by the public and the open-source community. Members of the MIPI Alliance enjoy benefits such as access to relevant licenses, and opportunities to participate in development activities, interoperability workshops and other events.
For information about MIPI Alliance membership, visit Join MIPI.
MIPI HTI was developed by the MIPI Debug Working Group and was originally released in July 2016. The most recent version of the specification, HTI v1.1, released in September 2021, introduces electrical enhancements to address more stringent signal-integrity requirements of link rates beyond 12.5 Gigabits per second (Gbps). These include requiring transmitter equalization, adjusting jitter generation and adding programming values for PHY clock frequencies at the higher link speeds.