A power management control and data bus to connect a SoC to one or more peripheral chips

Quick Facts

Physical layer


Fundamental features
  • High performance
  • Low power
  • Low EMI
Use Cases

Regulator control


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The MIPI System Power Management Interface, MIPI SPMI℠, specifies the hardware interface between baseband or application processors and peripheral components to support advanced power management techniques. The specification also reduces design costs and shortens time to market of mobile devices by simplifying the interconnection of devices from different manufacturers. It is used in smartphones, tablets, and other portable devices.

The MIPI System Power Management Interface is a two-wire serial interface that uses CMOS I/Os for the physical layer. The interface connects the integrated power controller of a system-on-chip (SoC) processor system with one or more power management IC voltage regulation systems. The interface can be used to accurately monitor and control processor performance levels required for a given workload or application and dynamically control the various supply voltages in real time based on the performance levels.

Features include a low pin count and low gate count, high speed, low latency, ability to support multiple processor devices on the same shared bus, priority management by traffic classes, and command acknowledgement.

The interface is developed by the MIPI Alliance System Power Management Working Group. The current release, v2.0, was released in 2012.

Note: The specification is available only to MIPI Alliance members. For information about joining MIPI Alliance, visit Join MIPI.

Get the Specification

Member version


Current Version: 

v2.0 (August 2012)