MIPI Debug Over I3C℠

Developed by: Debug Working Group

A technology for using MIPI debug protocols over MIPI I3C®


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General Info

The MIPI Debug Over I3C℠ specification, part of the "MIPI Debug Over" (MDO) family of specifications, is a bare-metal, minimal-pin interface for transporting debug controls and data between a debug and test system (DTS) and a target system (TS). The specification uniquely handles the network topology in a dynamic fashion, making it perfectly suited as a flexible and scalable debug and test specification for systems that enable mobile, the Internet of Things (IoT), automotive and other use cases.

MIPI Debug Over I3C allows system designers to efficiently and dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components across a system of any size via the low-bandwidth MIPI I3C® interface, which requires a minimal set of pins.


Specification Highlights

Debug Over I3C provides mechanisms to perform debug by using an I3C bus and describes the communication between a DTS and a TS over that I3C bus. This communication is used for:

  • Basic debug control, such as halt mode debugging of processors; and/or
  • Tracing, where streams of data are emitted from a TS to be decoded and analyzed in a DTS.

The Debug Over I3C specification extends the MIPI I3C specification by defining the reserved debug extensions in the I3C specification. Debug Over I3C allows for different designs where the I3C bus could be shared with non-debug communication. Whether the I3C bus is shared or dedicated for debug, the specification also allows for different DTS access points and allows for an externally connected DTS. The ability for an I3C bus to have multiple controller-capable devices allows the DTS to be connected as either the primary controller (usually with dedicated debug I3C buses) or as a secondary controller (usually with shared I3C buses).


Legacy Debug Solutions

Legacy debug solutions that are statically structured—such as JTAG/cJTAG, I2C and UART—lead to limited scalability for the accessibility of debug components/devices—for example, when they’re in low-power mode. MIPI Debug Over I3C overcomes these restrictions by building on key MIPI I3C features. MIPI Debug Over I3C delivers multi-component connectivity across either dedicated debug or shared bus topologies, requires only two wires, supports multiple entry points, and maintains a network even as components power down and off a network and then rejoin after powering back up.


Debug Over I3C Capabilities

MIPI Debug Over I3C offers key capabilities that make the interface scalable and flexible for use in applications throughout a product's lifecycle:

  • Debug over two pins
    • Single-ended
    • Push pull / open drain
  • Native I3C communication
    • Multi-component connectivity
    • Multiple entry points
    • Multi-lane support
    • Use of generic common command codes (CCCs) to include debug devices (e.g., hot join)
    • Debug-specific CCCs for configuration, function selection and action/event triggers and interrupts
    • Event indication and detection via in-band interrupt (IBI)
    • Specific mandatory data byte (MDB) values assigned to indicate debug IBIs
    • Standardized data-exchange mechanisms for predefined port-based communication
    • Use of high data rate (HDR) modes with improvements to increase transfer speed and efficiency
    • Support for timestamping
  • TS exposes multiple debug interfaces/ports from a single physical connection
  • DTS sends broadcast or directed action requests (halt, reset, etc.)
  • No special I3C controller hardware required

Diagrams & Tables

Debug Capabilities per Adjacent Industries »
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System Functional/Application Modules (click to enlarge image below)
The diagram below shows the standard MIPI debug architecture highlighting the functional area addressed by the Debug Over I3C specification.




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