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            1 min read

            MIPI Webinar: MIPI Debug for I3C: The Next Generation Debug Interface

            Picture of MIPI Alliance MIPI Alliance : 21 October 2020

            MIPI Debug for I3C
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            Webinar Overview

            Developed by MIPI Alliance’s Debug Working Group, MIPI Debug for I3CSM is a scalable, multi-mastering interface that allows system designers to dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components via the low-bandwidth MIPI I3C interface, which requires a minimal number of pins.

            In this webinar you'll hear how MIPI Debug for I3C addresses the shortcomings of current solutions based on JTAG/cJTAG, I2C and UART, which are statically structured and lead to limited scalability and accessibility of debug components/devices. The webinar also explains how MIPI Debug for I3C meets the requirements of new technologies such as 5G, and new markets such as IoT, where there are new and specific debug requirements that need to be addressed. 

            Aimed at debug experts, the webinar takes a “deep dive” to explain:
            • The key challenges associated with current debug solutions 
            • The goals set by the MIPI Debug working group when creating the MIPI Debug for I3C solution 
            • The benefits of using MIPI I3C as the basis of the MIPI Debug for I3C solution
            • The key features of MIPI Debug for I3C, including: interface topologies, Common Command Codes, in-band interrupts and network adaptor  

            Presenters

            Enrico Carrieri, Intel Corporation, Chair of the Debug Working Group

            Enrico recently received the 2019 Working Group Leadership Award in part for his coordination with the I3C Working Group to ensure the quality of the debug specification. He is also a frequent contributor to the MIPI Alliance blog, providing technical insights into MIPI debug specifications.

            Enrico will be joined by Matthew Schnoor, a debug architect at Intel and member of the MIPI Debug Working Group. Matthew has more than two decades of experience in various Intel business groups, primarily focused on software development, silicon validation and system debug architecture. He has enabled MIPI I3C to support MIPI Debug for I3C, and currently works across and within several MIPI working groups to help develop MIPI specifications in support of that goal.