MIPI D-PHY™

General Info

• Overview

  MIPI D-PHY℠ connects megapixel cameras and high-resolution displays to an application processor. It is a synchronous link, available in either embedded or forwarded clock modes, that provides high noise immunity and high jitter tolerance. MIPI D-PHY also offers low-latency transitions between high-speed and low-power modes.

  MIPI D-PHY is a popular physical layer (PHY) for cameras and displays in smartphones because of its flexibility, high speed, power efficiency and low cost. For these reasons, it has also been applied to many other use cases, such as drones, very large tablets, surveillance cameras and industrial robots. D-PHY also is used heavily in automotive applications, including camera-sensing systems, collision-avoidance radars, in-car infotainment and dashboard displays with the support of proprietary bridging solutions.

  MIPI D-PHY is developed by the MIPI D-PHY Working Group. The specification is available only to MIPI Alliance members. For information about joining MIPI Alliance, see Join MIPI.

• Capabilities

  Operation and available data rates for a link are asymmetrical due to camera and display application needs. The asymmetrical design of D-PHY significantly reduces the complexity of the link and makes it well-suited for display and camera use cases with one major data transmission direction, for example. Bi-directional and half-duplex operation are optional.

  MIPI D-PHY includes a fast bus turnaround (BTA), as well as an alternate low power (ALP) feature, which enables a link operation using only D-PHY’s high-speed signaling levels. These features enable applications of not only mobile devices, but also IoT devices operating over several meters at high speed. Also, these features enable an optional in-band control mechanism supported by the MIPI Camera Serial Interface 2 (MIPI CSI-2^®) v3.0 Unified Serial Link (USL).

• Latest Releases (v3.0 and v3.5)

  Version 3.0 doubles the data rate of D-PHY’s standard channel to 9 Gigabits per second (Gbps) and 11 Gbps for its short channel, enabling support for the latest ultra-high-definition displays and beyond. In tandem with the boost in data rate, D-PHY v3.0 introduces a Continuous-Time Linear Equalizer (CTLE) on the receiver side of a connection to maintain the interface’s superior power efficiency. D-PHY v3.0 is fully compatible with previous versions of the MIPI specification.

  The latest version of the specification, D-PHY v3.5, introduces an optional embedded clock mode, while remaining compatible with existing D-PHY electrical levels and supported channels. As part of the embedded clock enhancements, a 128-132b data encoding scheme and a clock data recovery block have been added. Forwarded clock remains an option in D-PHY v3.5, which is backward compatible with previous versions of the specification. Designers have the choice to use either or both clock modes in a system. Opting to use the embedded-clock mode with v3.5 frees a lane of traffic that otherwise would be required to carry the forwarded-clock signal. This means that v3.5 boosts the effective throughput of a D-PHY link.

  Version 3.5 of D-PHY also replaces the words “master” and “slave” (which MIPI has deprecated as technical terms), with “primary” and “secondary,” respectively.