A medium-speed, utility and control bus interface for connecting peripherals to an application processor in a range of mobile, IoT and automotive applications

Quick Facts

Key Highlights
  • Incorporates the key capabilities of I2C and SPI into an advanced, consolidated specification
  • Reduces pin count and signal paths
  • High performance
  • Very low power
  • Low electromagnetic interference (EMI)
  • Backward compatible with I2C


Physical Layer


Use Cases

Connect peripherals to an application processor in any mobile device
Simplify connecting and managing of multiple sensors in a device
MIPI Touch over I3C provides a converged interface option for processed and raw touch data
MIPI CCI over I3C offers faster, lower latency and more efficient camera control


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MIPI I3C® is a scalable, medium-speed, utility and control bus interface for connecting peripherals to an application processor, streamlining integration and improving cost efficiencies. It gives developers unprecedented opportunities to craft innovative designs for any mobile product—from smartphones, to wearables, to systems in automobiles.

MIPI I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a unified, high-performing, very-low-power solution and delivers a robust, flexible upgrade path to I3C for I2C and SPI implementers. While I3C v1.0 delivered new capabilities to integrate mechanical, motion, biometric, environmental and any other type of sensor, MIPI I3C v1.1 (now v1.1.1) built on that capability by adding new features for peripheral command, control and communication to a host processor over a short distance and system manageability.

MIPI I3C technology is implemented on a standard CMOS I/O. It uses a two-wire interface, which reduces pin count and signal paths to offer system designers less complexity and more flexibility. It can also be used as a sideband interface to further reduce pin count. MIPI I3C supports a typical data rate of 10 Megabits per second (Mbps) with options for higher-performance high-data-rate modes, offering a substantial leap in performance and power efficiency compared with previous options. The latest version provides for extensible use of extra bus lanes to increase the interface speed, enabling new use cases and future proofing the interface as speed requirements rise. The specification enables a diverse set of new applications:

  • Memory sideband channel
  • “Always-on” imaging
  • Server system management
  • Debug application communications
  • Touchscreen command and communications
  • Sensor device command, control and data transport
  • Power management

The specification is ideal for system-level implementers seeking a low-cost, off-the-shelf standardized bus solution with a small printed circuit board (PCB) footprint and a well-defined and readily available ecosystem of peripherals, sensors and applications.

Additional technical highlights include multi-controller support, dynamic addressing, command-code compatibility and a uniform approach for advanced power management features, such as sleep mode. It provides synchronous and asynchronous time-stamping to improve the accuracy of applications that use signals from various sensors. It can also batch and transmit data quickly to minimize energy consumption of the host processor.

The most recent specification, I3C v1.1.1, published in June 2021, contains several clarifications necessary for consistent interpretation of I3C v1.1, but does not introduce any new features. In addition, the new version replaces objectionable terms with ones that more accurately reflect the functions of technical devices.

To support developers, backward compatibility has been confirmed through multiple interoperability workshops, and two supporting specifications—DisCo for I3CSM and the I3C Host Controller Interface (MIPI I3C HCISM)—have been made publicly available. Further, an I3C HCI driver has been added to the Linux kernel, and a Debug for I3C specification was released in 2020.

MIPI I3C is developed by the MIPI Alliance I3C Working Group.

The full specification is available only to MIPI Alliance members. For information about joining MIPI Alliance, visit Join MIPI.

MIPI I3C Basic

MIPI I3C BasicSM is a subset of MIPI I3C that bundles the most commonly needed I3C features for developers and other standards organizations. The mobile ecosystem and broader system integrator community can efficiently use these capabilities as an alternative to I2C.

MIPI I3C Basic is available for implementation without MIPI membership and is intended to facilitate a royalty-free licensing environment for all implementers, as described within the specification.

The most recent version of I3C Basic dramatically enhances the specification’s speed and flexibility. I3C Basic v1.1.1 provides for extensible use of extra bus lanes to increase the interface speed to near 100 MHz. The new version includes two High Data Rate (HDR) modes—HDR Double Data Rate (HDR-DDR) and HDR Bulk Transport (HDR-BT)—designed to transfer more data at the same bus frequency. Another new feature, standardized target reset, improves I3C Basic’s ability to reset a specific peripheral device, enabling better recovery from error conditions. 

I3C Basic v1.1.1 also replaces offensive terms with ones that more accurately reflect the functions of technical devices. 

The specification is developed by the MIPI I3C Basic Ad Hoc Working Group.

MIPI I3C and I3C Basic Feature Comparison