D-PHY

Charter

The MIPI D-PHY Working Group, promoted from a subgroup in 2021, was created to develop a high-speed serial physical layer (PHY) specification that supports the requirements of camera and display applications in mobile and mobile-influenced product spaces such as handsets, wearables, the Internet of Things (IoT) and automotive. 

The MIPI D-PHY^℠ specification defines a clock-forwarded synchronous link with a dedicated clock lane and one or more scalable data lanes. The widely implemented interface is specifically designed to serve as the PHY transport for other MIPI higher-layer protocols, most notably MIPI CSI-2^® for cameras and MIPI DSI-2^℠ for displays.

Industry Need

The group’s D-PHY specification fulfills the industry's need for a flexible, high-speed low-power PHY solution that meets upcoming imaging and display interface requirements for mobile and mobile-influenced devices.

Accomplishments

The D-PHY Working Group is responsible for developing MIPI Alliance's first physical layer specification more than 15 years ago. Since that time, it has developed nearly a dozen versions of the specification, each adding new features or enhancements to support the ever-evolving requirements and applications of cameras and displays. The most recent version, v3.0, was released in 2021 and doubles the specification’s speed to 9 Gbps for the standard channel (and 11 Gbps for its short channel) to enable support for the latest ultra-high-definition displays and beyond.

The group has also developed a number of conformance test suites to help ensure device interoperability across vendor components.

Focus

The working group oversees the evolution of the D-PHY specification to meet the current and anticipated needs of higher-level applications, while providing backward compatibility to previously released versions of the specification. The group draws on guidance and input from its  stakeholders such as the MIPI Camera, Display and Test working groups. 

The scope of the D-PHY Working Group’s technical work includes: 

• PHY architecture development
• Transmitter/receiver system modeling
• Electrical specification for transmitter and receiver
• Interconnect modeling
• Start up and logic state machine development 
• Test mode development  
• Conformance test support