MIPI SWI3S™

The MIPI SoundWire I3S (SWI3S) specification, introduced in October 2025, defines a new 2-wire, scalable, low-power and noise-resilient audio streaming and control interface for modern audio systems. SWI3S eliminates the need for multiple dedicated lines for audio streaming, control and interrupts as required by legacy audio interfaces (e.g., TDM + I2C, I2S, HDA, MIPI SLIMbus).

SWI3S supports data rates up to 76 Mbps over a two-pin interface and provides the flexibility to either operate in forwarded bit clock single-ended (FBCSE) or differential low-voltage (DLV) signaling modes. The DLV PHY provides high noise immunity, low crosstalk and reduced EMI coupling, minimizing the need for heavy physical shielding even in densely integrated designs.

The specification’s physical-layer flexibility enables deployment across an exceptionally wide range of audio use cases, from ultra-compact, tightly packaged devices such as earbuds and wearables, to large-scale systems such as automotive audio networks requiring multi-meter link lengths. It provides comprehensive link management to configure, control, synchronize and transition between different power states. It also provides an audio-grade clock suitable for precise timing and synchronization. SWI3S supports dynamic control of audio and command channels, enabling always-on, low-power operation in use cases across mobile, consumer, and automotive platforms.

A SWI3S- based audio system may comprise one or more SWI3S links, each consisting of a SWI3S manager and up to 12 audio peripherals connected through a shared physical-layer interface. Each peripheral can support up to 32 data ports, each with up to 16 channels.

Its flexible architecture with support for both DLV and FBCSE PHYs, tiered topologies and mixed-signaling environments enables designers to optimize for performance, cost, EMI, and physical layout across a broad range of products. SWI3S provides the robustness, configurability and efficiency required by today’s complex audio system designs.

Use Cases

• Microphone arrays, speakers, amplifiers, haptic drivers, hearing aid coils
• Echo cancellation, noise suppression and beam forming
• Always on and low power designs
• High-fidelity and immersive audio
• Low-latency multichannel audio transfers
• Small, medium and large form factors

Key Features

• Transports audio data, control commands, interrupt signals, and synchronization information over unified two-pin link, minimizing pin count and interconnect complexity
• Supports both forwarded bit clock single-ended (FBCSE) and differential low-voltage (DLV) signaling modes. These options accommodate a wide range of link lengths, physical layouts, and EMI/EMC requirements, enabling both short-reach and long-reach system designs with high noise immunity and low electromagnetic coupling
• Achieves up to ~76 Mbps in DLV mode and approximately ~51 Mbps in FBCSE mode, providing ample bandwidth for multi-channel audio and control data streams
• Provides an audio-quality reference clock suitable for standard audio sampling frequencies (e.g., 44.1 kHz, 48 kHz, 96 kHz), enabling precise timing alignment and synchronous operation across peripheral devices and links
• Supports periodic payload delivery, including streaming of audio sample data between digital audio components with:
  • Multiple channels (supporting fan-out and fan-in configurations across devices)
  • Flexible data encodings (e.g., PDM, PCM )
  • Mixed or differing sample rates (e.g., 44.1 kHz and 48 kHz within the same system)
  • Flow-controlled transmission, allowing both source-controlled and sink-controlled modes
  • Low transmission latency, typically around 300 ns end-to-end
• Provides a dedicated in-band channel for control operations, such as register read/write transactions, status reporting and multi-data transfers (e.g., firmware updates)
• Supports in-band interrupt notifications, wake-up signaling and peripheral reset control, enabling intelligent event handling without extra GPIO lines
• Incorporates power-saving link states, including sleep/wake transitions and clock-pause modes, minimizing power consumption in always-on or idle system scenarios
• Supports peripheral low power states, allowing idle peripherals to enter dormant state

Supporting software components, MIPI DisCo Specification for SoundWire v1.0, and MIPI SoundWire Device Class for Audio v1.0 are available for public download.

The SWI3S specification was developed by the MIPI Audio Working Group and is available only to MIPI Alliance members. For information about joining MIPI Alliance, visit Join MIPI.