MIPI C-PHY℠ provides high throughput, a minimized number of interconnect signals and superior power efficiency to connect displays and cameras to an application processor. This is due to efficient three-phase coding that is unique to C-PHY. This efficiency minimizes the cost of system interconnect and also minimizes emissions to sensitive RF receiver circuitry that is often co-located with the multimedia interfaces.
C-PHY provides a physical layer for the MIPI Camera Serial Interface 2 (MIPI CSI-2®) and MIPI Display Interface 2 (MIPI DSI-2℠) ecosystems, enabling designers to scale their implementations to support a wide range of higher-resolution image sensors and displays, while keeping power consumption low. The specification can be used to connect low-cost, low-resolution image sensors, as well as high-performance sensors offering up to 60 megapixels and display panels offering 8K and higher resolution. C-PHY can be applied for many use cases and industry segments, including mobile, wearable technologies, the IoT, drones, personal computers and automotive.
MIPI C-PHY can coexist on the same device pins withMIPI D-PHY℠, so designers can develop dual-mode devices. Operating data rates for a link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs and also enables link operation using only C-PHY’s high-speed signaling levels. Bi-directional and half-duplex operation are optional.
MIPI C-PHY is developed by the MIPI C-PHY Working Group and is available only to MIPI Alliance members. For information about participating in MIPI Alliance, see Join MIPI.
MIPI C-PHY is an embedded clock link that provides extreme flexibility to reallocate lanes within a link. It also offers low-latency transitions between high-speed and low-power modes. MIPI C-PHY accomplishes this by departing from a conventional differential signaling technique on two-wire lanes and introducing three-phase symbol encoding of about 2.28 bits/symbol to transmit data symbols on three-wire lanes, or “trios,” where each trio includes an embedded clock. The specification supports symbol rates up to 6 Gigasymbols per second (Gsps), equivalent to 13.7 Gbps, over the standard channel and up to 8 Gsps over the short channel. Three trios operating at 6 Gsps achieve a peak data rate of about 41 Gigabits per second (Gbps) over a nine-wire interface. A Continuous-Time Linear Equalizer (CTLE) on the receiver enables operation at higher symbol rates.
MIPI C-PHY includes a fast bus turnaround (BTA), as well as an alternate low power (ALP) feature, which enables a link operation using only C-PHY’s high-speed signaling levels. These features enable applications of not only mobile devices, but also IoT devices operating over several meters at high speed. Also, these features enable an optional in-band control mechanism supported by the MIPI CSI-2 v3.0 Unified Serial Link (USL).
The newest version of MIPI C-PHY, version 2.1, introduces a 64-bit PHY Protocol Interface (PPI) to provide the option for a wider bus between the physical interface and a chip’s core logic for better support of higher-performance applications. C-PHY v2.1 is fully compatible with previous versions of C-PHY.