A physical layer for high-performance, cost-optimized cameras and displays

Quick Facts

Specs Supported

Supports MIPI CSI-2 and MIPI DSI-2 applications and high-speed/low-power interfaces

Fundamental features
  • High performance
  • Low power
  • Low EMI
Use Cases

Smartphone cameras and displays

Smart watch displays

In-sight (glass) products

In-car infotainment and dashboard displays

Automotive camera and radar sensors

Industries

Icon of a Smart PhoneIcon of a TabletIcon of a laptopIcon of an AutomobileIcon of a cloud with the letters IoT inside.Icon of a cameraIcon of a Smartwatch

Overview

MIPI C-PHY provides high-throughput performance over bandwidth-limited channels to connect displays and cameras to an application processor. It provides a PHY for the MIPI Camera Serial Interface (MIPI CSI-2) and MIPI Display Interface (MIPI DSI-2) ecosystems, enabling designers to scale their implementations to support a wide range of higher-resolution image sensors and displays, while keeping power consumption low. It can be used to connect low-cost, low-resolution image sensors, sensors offering up to 60 megapixels, as well as display panels offering 4K and higher resolution. It can be applied for many use cases and industry segments, including mobile, wearable technologies, the Internet of Things (IoT), drones, personal computers and automotive.

MIPI C-PHY is an embedded clock link that provides extreme flexibility to reallocate lanes within a link. It also offers low-latency transitions between high-speed and low-power modes. MIPI C-PHY accomplishes this by departing from a conventional differential signaling technique on two-wire lanes and introducing three-phase symbol encoding of about 2.28 bits/symbol, to transmit data symbols on three-wire lanes, or “trios,” where each trio includes an embedded clock. Three trios operating at 6 Gsym/s achieve a peak data rate of about 41 Gbps over a nine-wire interface.

MIPI C-PHY can coexist on the same device pins with MIPI D-PHY, so designers can develop dual-mode devices. Operation and available data rates for a link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs. Bi-directional and half-duplex operation are optional.

Released September 2019: C-PHY v2.0. This version adds support for symbol rates up to 6 Gsps over the standard channel and up to 8 Gsps over the short channel, support for an RX equalization, support for a fast BTA, an in-band control signaling option, along with the support for medium channel lengths to suit IoT applications. This version of C-PHY v2.0 is targeted to be used along with MIPI CSI-2 v3.0.

MIPI C-PHY is developed by the MIPI PHY Working Group and is available only to MIPI Alliance members. For information about joining MIPI Alliance, see Join MIPI.

Get the Specification

Versions

Current Version: 

v2.0 (September 2019)