MIPI Debug for I3C℠

General Info

• Overview

  MIPI Debug for I3C^SM is a bare-metal, minimal-pin interface for transporting debug controls and data between a debug and test system (DTS) and a target system (TS). The specification uniquely handles the network topology in a dynamic fashion, making it perfectly suited as a flexible and scalable debug and test specification for systems that enable mobile, the Internet of Things (IoT), automotive and other use cases.

  MIPI Debug for I3C allows system designers to efficiently and dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components across a system of any size via the low-bandwidth MIPI I3C^® interface, which requires a minimal set of pins.

  MIPI Debug for I3C was developed by the MIPI Debug Working Group. All MIPI debug and trace specifications, including MIPI Debug for I3C, are available for download and use by the public and the open-source community. Members of the MIPI Alliance enjoy benefits including access to relevant licenses and opportunities to participate in development activities, interoperability workshops and other events.

  For information about MIPI Alliance membership, visit Join MIPI.

• Legacy Debug Solutions

  Legacy debug solutions that are statically structured—such as JTAG/cJTAG, I²C and UART—lead to limited scalability for the accessibility of debug components/devices—for example, when they’re in low-power mode. MIPI Debug for I3C overcomes these restrictions by building on key MIPI I3C v1.1 features. MIPI Debug for I3C delivers multi-component connectivity across either dedicated debug or shared bus topologies, requires only two wires, supports multiple entry points, and maintains a network even as components power down and off a network and then rejoin after powering back up.

• Key Capabilities

  MIPI Debug for I3C offers key capabilities that make the interface scalable and flexible for use in applications throughout a product's lifecycle:

  • Debug over two pins
    • Single-ended
    • Push pull / open drain
  • Native I3C communication
    • Multi-component connectivity
    • Multiple entry points
    • Use of generic common command codes (CCCs) to include debug devices (e.g., hot join)
    • Debug-specific CCCs for configuration, function selection and action/event triggers and interrupts
    • Event indication and detection via in-band interrupt (IBI)
    • Specific mandatory data byte (MDB) values assigned to indicate debug IBIs
    • Standardized data-exchange mechanisms for predefined port-based communication
  • TS exposes multiple debug interfaces/ports from a single physical connection
  • DTS sends broadcast or directed action requests (halt, reset, etc.)
  • No special I3C controller hardware required

• Diagrams & Tables

  Debug Capabilities per Adjacent Industries

  Click to Enlarge