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MIPI Webinar: A Deep Dive into MIPI Debug for I3C

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Webinar Overview

Developed by MIPI Alliance’s Debug Working Group, MIPI Debug for I3C SM is a scalable, multi-mastering interface that allows system designers to dynamically debug and test application processors, power management integrated circuits, modems, and other power-managed components via the low-bandwidth MIPI I3C® interface, which requires a minimal number of pins.

Following on from the recent MIPI webinar –  MIPI Debug for I3C: The Next Generation Debug Interface (view recording) – this webinar goes to the next level of detail to provide a technical “deep dive” into the specification.

Aimed at debug experts who are already familiar with the MIPI debug framework, the webinar covers:

  • MIPI I3C bus topologies and configuration with Debug for I3C
  • Debug network adaptors: Key concepts and how to enable MIPI debug protocols
  • New debug CCCs (Common Command Codes) used for configuration and control
  • Session management and debug resets
  • Use of I3C IBIs (in-band interrupts) for status and data payload delivery


Matthew Schnoor, Debug Architect, Intel Corporation & Member of MIPI Debug Working Group

Matthew is a debug architect at Intel and member of the MIPI Debug Working Group. Matthew has more than two decades of experience in various Intel business groups, primarily focused on software development, silicon validation and system debug architecture. He has enabled MIPI I3C to support MIPI Debug for I3C, and currently works across and within several MIPI working groups to help develop MIPI specifications in support of that goal.