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MIPI DSI-2 v2.1 Update Utilizes MIPI D-PHY’s New Embedded Clock Feature

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To address the ever-increasing resolution and bandwidth required by today’s video-rich applications, the Display Working Group has upgraded MIPI Display Serial Interface 2 (DSI-2) to take advantage of the optional embedded clock feature introduced in the new MIPI D-PHY v3.5. physical layer specification.

Embedded clocking is especially valuable for applications with stringent requirements around electromagnetic interference (EMI), power consumption and pin count, such as cellular phones, headsets and other devices that leverage location identification. To support embedded clocking with DSI-2, MIPI added the D-PHY PHY-Protocol Interface (PPI) error signaling to reflect new receiver (RX) error status registers, as well as a protocol design that requires no change to the existing, stable DSI-2 data types and command language. DSI-2 v2.1 includes augmented PPI training in place of clock-lane to data-lane deskewing, which would not be necessary for an embedded clocking system.

Released in 2016, DSI-2 builds on the original DSI specification introduced more than 15 years ago. Since then, DSI-2 has been meticulously developed to support increasingly rich visual experiences at the lowest possible power consumption across a gamut of display applications—from high-resolution (8K and beyond), high-frame-rate (90 Hz and beyond) video modes, to graphical user interface “command” modes, and low-power and ultra-low-power modes. The specification is highly scalable and flexible, capable of supporting any resolution and configurable with one or multiple data lanes, which ultimately reduces both design cost and time to market.



The Display Working Group also has delivered an update to the MIPI Display Command Set (MIPI DCS), a standardized command set for control of DSI-2 displays to simplify DSI-2 use, development and interoperability across product implementations.

The new v2.0 of DCS adds commands for automotive and Internet of Things (IoT) applications, particularly commands for passing the Frame Service Extension Data (FSED) structure, which will be included in the forthcoming MIPI Display Service Extensions (MIPI DSE) v1.1 specification to support optional advanced functional safety, as well as commands for accessing the DSE and MIPI A-PHY® control register spaces.

The DCS v2.0 specification contains a register mailbox architectural design that is employed by the abovementioned function and can be expanded to comprehend for security support aligned with both a future DSE update and the upcoming MIPI Security Framework. Finally, DCS v2.0 offers clarifications and updates to the Adaptive Refresh Panel (ARP) commands to improve performance for variable refresh rate (VRR) OLED displays.

Implementing MIPI DCS reduces time to market and design cost of devices by offering a standardized command set for all setup, control and test functions, including the control of settings such as resolution, width and brightness. The command set also simplifies the addition of new product features, such as larger or additional displays, due to the extensible nature of MIPI specifications.

Both DSI-2 and DCS support the Video Electronics Standards Association (VESA®) Display Stream Compression (DSC) and VESA Display Compression-M (VDC-M) standards.


Shaping Ongoing Innovation

The MIPI Display Working Group continues to develop widely deployed display specifications for a broad range of application areas, including mobile, gaming, automotive, personal computer (PC)/mobile compute, IoT, augmented reality (AR)/virtual reality (VR), wearables and others.

To learn more and contribute to the ongoing refinement of DSI-2, DCS and other display specifications, MIPI members are invited to join the MIPI Display Working Group.