The smaller and more power-constrained systems being developed today for the Internet of Things (IoT), mobile devices, automotive and other use cases demonstrate the value of low-bandwidth interfaces for debug and trace. At the same time, the flexibility and scalability that these new use cases require have revealed crucial shortcomings in legacy low-bandwidth interfaces that are structured statically, such as JTAG/cJTAG, I2C and UART.
A recent MIPI Alliance press release details how an understanding of these market challenges fueled development of MIPI Debug for I3C v1.0. The MIPI Debug Working Group developed a specification that uniquely handles debug and trace in a dynamic fashion. Building on the MIPI I3C v1.1 (and MIPI I3C Basic v1.0) utility and control bus, system designers are able to efficiently debug and test application processors, power management integrated circuits, modems and other power-managed components across all systems via the low-bandwidth MIPI I3C interface. The new specification has key distinctions that make it well-suited for the use cases and challenges designers and developers are facing today:
Requiring a minimal set of pins (i.e., two wires)
Enabling multi-component connectivity
Supporting scenarios throughout a product's lifecycle
Maintaining a network even as components power down and off a network and then rejoin after powering back up
The press release further details how the new interface transports debug controls and data between the debug and test system (DTS) and a target system (TS).
To find out more about the features and benefits of Debug for I3C v1.0, the Debug Working Group is hosting a webinar on Oct. 21, 2020, at 11 a.m. EDT, 8 a.m. PDT. The event will also offer an opportunity to learn about the rich MIPI debug and trace ecosystem that has been built to provide solutions for the entire lifecycle of embedded systems.