MIPI DevCon Taipei—scheduled for 18 October 2019 at the Grand Hyatt Taipei—is a prime opportunity for technical training on MIPI’s comprehensive portfolio of specifications to interface chipsets and peripherals in mobile-connected devices. System architects, engineers, designers, test engineers, engineering managers, and business and marketing executives are encouraged to come to learn the latest on how MIPI technology is facilitating new capabilities within mobile and across markets such as automotive, the Internet of Things (IoT), wearables, industrial and augmented/virtual reality (AR/VR).
Two technical sessions will examine the features available in forthcoming versions of MIPI I3C® and MIPI RFFESM. The I3C session will look at the efforts MIPI Alliance is taking to advance I3C for broad, long-term adoption across multiple industries and usages. The RFFE session will address how this specification aims to meet new 5G control timing requirements.
A session on next-generation displays for AR/VR and other sectors (such as mobile and automotive) will look at VDC-M—VESA’s newest display interface compression standard—and how it offers unprecedented levels of visually lossless compression when used with MIPI DSI-2SM transport. Attendees will hear an overview of the VDC-M algorithm and concrete use cases.
Also of interest, the event will include a session on the MIPI Discovery and Configuration Creation Tool and how “DisCo” reduces the effort required to develop platform firmware images and time to debug firmware/software. The MIPI DisCo tool simplifies such processes by using device-specific (SoundWire® Master, I3C HCISM, etc.) templates in ACPI source language (ASL).
Reliable, efficient conformance test and characterization of MIPI PHYs will be the focus of a technical session summarizing lessons learned from first-hand experience with the testing of high-speed digital interconnect busses. "PHY Testing Challenges and Opportunities: The Need For a Smart Testing Approach," will address complex, high-speed electrical PHY layer receiver conformance tests, along with transmitter, cable and protocol tests and DUT bring-up and debugging.
Another technical presentation will review an investigation of the influence of random jitter on MIPI C-PHYSM's high-speed timing. Not only can the study provide a reference for MIPI C-PHY designers, it also could help inform ongoing development of the MIPI C-PHY specification with regard to signal impairment caused by random jitter.