I3C offers dynamic address assignment, Slave-initiated communication, and significantly higher communication speeds than I²C.
Yes, a number of companies have released products which feature integrated I3C Master and I3C Slave support. Other companies offer IP blocks and associated verification software for adding I3C Bus support into various integrated circuit designs. Some companies also offer protocol analyzers and verification hardware to help analyze I3C Bus traffic for testing and development.
Since this document cannot provide a comprehensive list of such products, those who are interested in learning more about products that support or enable I3C should contact MIPI Alliance.
The power consumption per bit transfer in all I3C modes is more efficient than I²C, due to the use of push-pull (vs. open-drain) and strong pull-up signaling.
Further, I3C can save considerable device power through higher data rates (because the device can be put back to sleep sooner), built-in configuration and control (without intruding on the main communication protocols), in-band interrupt (IBI) as a low-cost wake mechanism, and the ability for Slaves to shut down all internal clocks while still operating correctly on the I3C Bus.
While I²C has seen wide adoption over the years, it lacks some critical features – especially as mobile and mobile-influenced systems continue to integrate more and more sensors and other components. I²C limitations worth mentioning include: 7-bit fixed address (no virtual addressing), no in-band interrupt (requires additional wires/pins), limited data rate, and the ability of Slaves to stretch the clock (thus potentially hanging up the system, etc.). I3C aims both to fix these limitations and to add other enhancements.
I3C was initially intended for mobile applications as a single interface that can be used for all digitally interfaced sensors. However it is now intended for all mid-speed embedded and deeply embedded applications across sensors, actuators, power regulators, MCUs, FPGAs, etc. The interface is also useful for other applications, as it offers high-speed data transfer at very low power levels while allowing multi-drop, which is highly desirable for any embedded system.
No, I3C Masters control an active pull-up resistance on SDA, which they can enable and disable. This may be a board-level resistor controlled by a pin, or it may be internal to the Master.
I3C has two signal lines: Data (SDA) and Clock (SCL).
MIPI I3C carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides the higher data rates, simpler pads, and lower power of SPI. I3C then adds higher throughput for a given frequency, in-band interrupts (from Slave to Master), dynamic addressing, advanced power management, and hot-join.
The main purpose of MIPI I3C is threefold:
- To standardize sensor communication,
- To reduce the number of physical pins used in sensor system integration, and
- To support low power, high speed, and other critical features that are currently covered by I²C and SPI.
MIPI I3C’s purpose is now widening to cover many types of devices currently using I²C/SMbus, SPI, and UART.
The official name is MIPI Alliance Improved Inter Integrated Circuit.