PCIe tunneling is not presently supported. MIPI A-PHY is highly asymmetric, with high bandwidth in one direction and low bandwidth in the other (i.e., 16 Gbps in one direction and 100Mbs in the other for A-PHY v1.0).
With STQ /HSD dual lanes, yes. This is now being developed with A-PHY v1.1, and even higher speeds will be addressed in future releases using similar cabling.
Startup time is up to 100ms.
Nothing in the specification prevents using the sync signal as the clock.
MIPI A-PHY can deliver:
- Power: 6W max
- Voltage: 8V-13V
- Current: 0.75A MIN
There is an active mode consisting of Normal state and Start-up state; a non-active mode consisting of Sleep state and Power-up state and a Test mode.
The A-PHY Data Link Layer is a protocol-agnostic layer that performs scheduling, prioritization and forwarding of A-Packets.
- Each protocol adaptation layer has at least one A-PHY protocol interface (APPI) connection to the A-PHY Data Link Layer.
- The A-PHY Data Link Layer may be connected to multiple protocol adaptation layers using a single local function.
- The A-PHY Data Link Layer may have a single A-PHY network function connected to it, or multiple A-PHY network functions.
A-PHY layer has the following features and functions:
Features for a robust system include:
- High-speed downlink and aggregation to support multiple 4K cameras and displays
- Asymmetric high-speed link with fixed low latency ~6μs for Gear 5, resulting in a PER of less than 10-19 (which is equivalent to 1 packet error in ~10,000 car-lifetimes)