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            1 min read

            JEDEC UFS, MIPI UniPro and MIPI M-PHY: A Winning Combination Enabling State-of-the-Art Flash Storage Solutions

            Picture of MIPI Alliance MIPI Alliance : 19 February 2024

            MIPI UniPro MIPI M-PHY
            Featured Image

            JEDEC UFS, MIPI UniPro and MIPI M-PHY Webinar

            Presented on 15 February 2024, this webinar focuses on how JEDEC UFS leverages MIPI M-PHY® and MIPI UniPro® to provide its interconnect layer, and how its most advanced release, UFS 4.0, leverages the recent versions of these MIPI specifications to double its interface bandwidth. 

            Learn more about:

            • How the latest M-PHY v5.0 physical-layer specification addresses increasing data rate requirements and provides engineers with design flexibility for advanced applications. This part of the presentation will detail how a new speed gear — "High Speed Gear 5" (HS-G5) at 23.32 Gigabits per second (Gbps) — doubles the potential data rate per lane compared with the previous specification.
            • How the latest UniPro v2.0 transport layer specification for interprocessor communication (IPC) supports a doubling of the physical-layer data rate by increasing packet payload length and decreasing communication latency through the addition of high-speed linkup.
            • How the latest, and most advanced interaction of UFS, 4.0, leverages M-PHY v5.0 and UniPro v2.0 to double the UFS interface bandwidth and enable up to ~4.2 GB/s for read and write traffic. This part of the presentation will detail key enhancements delivered within both UFS 4.0 and UFS 3.1.

             

            Presenters

             

            Sérgio Silva, Program Engineering Manager, Synopsys; Chair of the MIPI M-PHY Working Group

            As a program engineering manager for Synopsys, Sérgio Silva has extensive experience in multiple SerDes protocols such as PCIe, USB-C/DisplayPort and, of course, M-PHY. He currently serves as chair of the MIPI M-PHY Working Group and has been with the MIPI M-PHY Working Group since v3.0 definition, providing support to the electrical, protocol and testing aspects of the specification.

            Sergio Silva
             

            Ramesh Hanchinal, ASIC Digital Design Manager, Synopsys; Chair of MIPI UniPro Working Group

            As an ASIC digital design manager at Synopsys, Ramesh concentrates on PCIe, MIPI UniPro and M-PHY, universal verification methodology (UVM) and system Verilog. He currently serves as chair of the MIPI UniPro Working Group and was a technical author of MIPI UniPro v1.61 and v1.8.

            Ramesh Hanchinal
             

            Bruno Trematore, Chief Engineer, KIOXIA, Co-Chair of the JEDEC UFS Technical Group

            Bruno Trematore is a chief engineer responsible for embedded memory standardization for KIOXIA and is co-chair of the JEDEC UFS TG. He also serves as liaison between MIPI and JEDEC on behalf of JEDEC JC-64.1.

            Bruno Trematore