A compliant I3C Device that can fulfill the role of Target is required to:

  • Accept an assigned Dynamic Address from the Active Controller, using any or all of the supported methods (i.e., ENTDAA, SETDASA, and/or SETAASA; see Q18.7, "Which Dynamic Address Assignment CCCs is a Device required to support?" and specification Section 5.1.4.2). Note that some of these methods require an I2C Static Address.
    • If the ENTDAA method is supported, then the Device must have a MIPI Provisional ID and a MIPI-compliant DCR.
  • Detect when it is addressed by its assigned Dynamic Address in SDR Mode, and respond to any I3C Private Read or Private Write transfers (as appropriate for the I3C content protocol).
  • Respond to the mandatory CCCs for Targets, including ENEC, DISEC, RSTDAA, GETCAPS, GETSTATUS, and RSTACT
    • Note that other CCCs might also be conditionally required, such as GETPID, GETBCR, and (if ENTDAA is supported) GETDCR.
  • Detect when the Active Controller enters any HDR Mode, using the ENTHDR0 – ENTHDR7 CCCs, and either:
    • If the Target supports that HDR Mode: Monitor Bus activity according to the HDR Mode’s signaling and coding, and respond appropriately to any HDR Read or HDR Write transfers that are addressed to the Device’s Dynamic Address.
      Or:
    • If the Target does not support that HDR Mode: Ignore all activity on the Bus until the Device sees the HDR Exit Pattern (per specification Section 5.2 and Section 5.2.1).
  • Implement Error detection and recovery methods for an I3C Target, including Error Types TE0 through TE5 per specification Section 5.1.10.
FAQ Type: 
I3C