Note: This question does not apply to I3C Basic v1.0.
Per Q21.3 ("When is the Pull-Up resistor enabled?") and Q21.4 ("Is a High-Keeper needed for the I3C Bus?"), the Controller manages its Pull-Ups to allow for ACK/NACK as well as Bus
Turnaround. The Controller sends the HDR-DDR Command Word with SDA in Active drive (i.e., Push-Pull mode) for the Command Word until the last Parity bit (i.e., PA0), which is initially driven High. Before the falling edge of C10 cycle, the Controller prepares for the Target to respond by disabling Push-Pull mode and engaging an appropriate Pull-Up to keep SDA at High. After the rising edge of the next C1 cycle, the addressed Target has the opportunity to either:
- Accept the DDR Write or Read by pulling SDA to Low, or
- Ignore the DDR Write or Read by leaving SDA at High
Note: This scheme is similar to SDR Mode’s ACK/NACK scheme for the Address Header, where SDA is “Parked” at High and the Target can pull SDA to Low to acknowledge the transaction.
The Controller should use the appropriate Pull-Up to enable Bus Turnaround or acceptance by the Target. For most use cases, the Open-Drain class Pull-Up is recommended; however, the High-Keeper could also be used, based on system design factors per specification Section 184.108.40.206. In either case, the Target must be able to pull SDA to Low before the falling edge of the C1 cycle.
Note that the next C1 cycle is the start of the first HDR-DDR Data Word (if the Target accepts the transfer) and the PRE1 bit (i.e., the rising edge of the C1 cycle) is always 1’b1 per Section 5.2.2. Using this scheme, the Target’s response determines the preamble bits:
- Bits 2’b10 indicate a Target ACK (i.e., accepting the DDR Write or Read) which starts the first HDR-DDR Data Word; or
- Bits 2’b11 indicate a Target NACK (i.e., ignoring the DDR Write or Read). The Controller then drives the HDR Restart Pattern or HDR Exit Pattern.