This mechanism allows an I3C Target to delay sending a complete HDR-BT Data Block during an HDR-BT Read transfer, for situations where the I3C Target or its inner system was unable to fully prepare enough data bytes to fill a Data Block as part of the Read transfer in HDR-BT Mode.

In I3C v1.1, the HDR-BT Data Block Delay mechanism was called the “Stall (delay) mechanism” and was not fully defined. Additionally, the name “Stall (delay)” was too easily confused with other I3C defined behaviors in which SCL clock stalling is permitted (i.e., stalling by the I3C Controller is allowed, but never stalling by an I3C Target). The confusion occurred because this HDR-BT mechanism is fundamentally different from SDR Mode SCL clock stalling, and I3C forbids SCL clock stalling in HDR-BT Mode

The I3C v1.1.1 specification addresses this confusion by renaming the mechanism to more accurately reflect its definition, and by adding clearer, more complete normative details. In addition, the name of parameter “tBT_STALL” was changed to “tBT_DBD”.

During an HDR-BT Read transfer, the Data Block Delay mechanism allows the I3C Target to transmit either:

  • A valid Data Block, which is not intended to be the last such Data Block, if the Target has a full 32 bytes of data to transmit; or
  • A single Delay byte, indicating that the Target is not yet ready to transmit a Data Block and that the I3C Controller should therefore continue the Read if it wishes to receive more data.

This Delay byte differs from a valid Transition_Control byte (i.e., the first byte of an HDR-BT Data Block). The I3C Target may defer sending a Data Block (i.e., by sending a Delay byte up to a maximum of 1024 times) at any point of a Read transfer, before it must terminate the Read transfer. The I3C Controller also has the opportunity either to continue waiting (i.e., receiving more Delay bytes until the I3C Target has enough data), or to terminate the Read transfer at its discretion.

This mechanism does not allow an I3C Target to delay sending either the CRC Block or the Last Data Block (e.g., one that might have “ragged” data).

The I3C Controller determines whether the I3C Target may use the Data Byte Delay mechanism. The Controller indicates this in the Control byte of the HDR-BT Header Block that starts each HDR-BT Read transfer.

  • If the I3C Target supports this mechanism and chooses to use it for this transfer, then the Target may use the mechanism if needed.
  • If the I3C Target does not support this mechanism, or if the I3C Controller has indicated that the Data Byte Delay is not permitted, then the I3C Target must not use this mechanism, in case it encountered a situation where it was unable to fully prepare enough bytes to fill a Data Block. In such a situation, the I3C Target might be forced to end the HDR-BT Read transfer early (i.e., by sending incomplete data).

This mechanism is primarily useful when the I3C Controller controls the SCL clock during the HDR-BT Read transfer, as the I3C Target would otherwise not have a method for indicating that the transfer should be slowed to match the actual rate of Data Blocks that it can reasonably produce (i.e., from its inner system that might provide the data bytes).

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