For those involved in debug and trace projects, one of the fundamental challenges is how to extract greater volumes of trace data from ever more complex devices, using ever-increasing higher-speed serial interfaces. This challenge is driven by the product of more—more data being transmitted inside devices, more functions happening at once on a die, and more components being integrated within devices. And the challenge is universal regardless of the application area—whether it's the Internet of Things (IoT), automotive, 5G or other areas.
To address this challenge, earlier this year the MIPI Debug Working Group introduced v1.1 of MIPI High-Speed Trace Interface (MIPI HTISM). This update introduces key electrical enhancements to satisfy the more stringent signal-integrity requirements of trace interfaces with speeds beyond 12.5 Gigabits per second (Gbps).
Role of MIPI HTI
MIPI HTI, initially released in 2016, is part of a suite of MIPI debug and trace specifications that facilitate standardized methods of debugging for scalability, simplicity, cost-effectiveness and vendor choice.
HTI defines how to transport trace information over high-speed serial interfaces, utilizing the low-level-physical, high-speed portions of interfaces such as PCI Express®, VESA DisplayPort™, HDMI® or USB in a bare-metal environment. It transports one of two trace protocols:
MIPI Trace Wrapper Protocol (MIPI TWPSM), a protocol for integrating multiple source trace streams into one trace stream by which system-unique identifications are assigned to encapsulated source byte streams
HTI provides higher transport bandwidth with fewer I/O pins compared with parallel interfaces, and it is complementary to MIPI Parallel Trace Interface (MIPI PTISM), which is available to designers who prefer parallel lines for multiple data signals.
Importance of trace reliability
Reliability is crucial in trace because any lost data could include important debug data associated with crucial system functionality and behavior issues, and trace reliability can be jeopardized by electrical issues at higher speeds.
MIPI HTI v1.1 addresses this concern by tightening up the electrical properties of the interface via key enhancements such as requiring transmitter equalization, adjusting jitter generation and adding programming values for the PHY clock frequencies at higher link speeds. Refining the transmitter electrical properties in these ways ensures trace reliability at higher rates such as 16 and 20 Gbps.
At the same time, these enhancements don't impact legacy trace solutions running at 12.5 Gbps and below, so designers can continue to rely on their existing trusted tooling. The updated specification delivers not only scalability beyond 12.5 Gbps, but also backward compatibility with lower-speed implementations of HTI and its Aurora 8B/10B-protocol serial communications between a target system and debug test system. Backward compatibility is of particular importance to HTI users because of the MIPI interface’s established ecosystem around its predecessors, such as ARM’s HSSTP.
With trace interface speeds continuing to increase, the group is already considering where the HTI specification may go next. It's clear that the next update may require fundamental changes to ensure reliable trace connections at still even higher speeds of 20 Gbps and beyond. It’s an ongoing challenge—but one the members of the MIPI Debug Working Group will continue to address in coming years.