Latest Version of C-PHY Introduces Support for 18-Wirestate Mode Encoding Option

MIPI C-PHY™, the ternary-based, high-performance, low-power and low electromagnetic interference (EMI) interface specification for connecting cameras and displays, recently got an upgrade to v3.0. This latest version introduces support for an 18-Wirestate mode encoding option, which can increase the maximum performance of a C-PHY lane by approximately 30 to 35 percent. The encoding option provides sufficient throughput to support the next generation of high-resolution, high-fidelity image sensors for a range of forward-looking applications.

C-PHY Overview

MIPI C-PHY supports the MIPI Camera Serial Interface 2 (MIPI CSI-2®) and MIPI Display Serial Interface 2 (MIPI DSI-2™) ecosystems in low-power, high-speed applications for the typical interconnect lengths found in mobile, PC compute and IoT applications.

It provides high throughput, a minimized number of interconnect signals and superior power efficiency to connect cameras and displays to an application processor. This is due to efficient three-phase coding unique to C-PHY that reduces the number of system interconnects and minimizes electromagnetic emissions to sensitive RF receiver circuitry that is often co-located with C-PHY interfaces.

The specification also offers flexibility to reallocate lanes within a link because C-PHY functions as an embedded clock link.

C-PHY is flexible and efficient because it can coexist on the same device pins as MIPI D-PHY™, so designers can develop dual-mode devices. Operating data rates for a bidirectional link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs and enables link operation using only C-PHY’s high-speed signaling levels.

New in Version 3.0

The new encoding option in C-PHY v3.0, 32b9s, transports 32 bits over nine symbols while maintaining MIPI C-PHY’s industry-leading low EMI and low power properties. For camera applications, the new mode enables the use of lower symbol rates or lane counts for existing use cases, or higher throughput with current lane counts to support new use cases involving very high-end image sensors, such as next-generation prosumer video content creation on smartphones, with high dynamic range (HDR), smart region-of-interest detection and advanced motion vector generation.

Support for C-PHY v3.0 was included in the most recent MIPI CSI-2 v4.1 embedded camera and imaging interface specification, published in April 2024. C-PHY v3.0 is backward-compatible with previous C-PHY versions.

New Developments in D-PHY

Significant development work is also continuing on MIPI's other primary shorter-reach physical layer, MIPI D-PHY.

D-PHY v3.5, released in 2023, includes an embedded clock option for display applications, while the forthcoming v3.6 specification will expand embedded clock support for camera applications, targeting PC / client computing platforms.

The next full version, v4.0, will further expand D-PHY’s embedded clock support for use in mobile and beyond-mobile machine vision applications and further increase D-PHY’s data rate beyond its current 9 Gbps per lane.

C- and D-PHY Channel Analysis Study for Longer Channel Lengths

MIPI Alliance last year conducted a comprehensive channel signal analysis study to document the longer channel lengths of both C- and D-PHY. The resulting member application note, "Application Note for MIPI C-PHY and MIPI D-PHY IT/Compute," demonstrated that both C-PHY and D-PHY can be used in larger end products such as laptops and all-in-ones with minimal or no changes to the specifications as originally deployed in mobile phones or tablets, or for even longer lengths, by operating at a reduced bandwidth.

To learn more and participate in the ongoing development of C-PHY and D-PHY, MIPI Contributor members are invited to join the C-PHY Working Group and D-PHY Working Group.