7 min read
MIPI Alliance Partners with embedded world Conference To Offer Dedicated MIPI Education Tracks
Sharmion Kerley, MIPI Director of Marketing and Membership : 21 February 2023
MIPI Alliance specifications will be in the spotlight next month at the 21st annual embedded world Exhibition & Conference, with two dedicated MIPI education tracks and nine total sessions focused on MIPI specifications.
The event, scheduled for 14-16 March in Nuremberg, Germany, will convene researchers and developers, industry and academia from all disciplines of embedded system development, from fundamental technologies to development processes and special fields of applications. This is the first year that MIPI Alliance has formally participated in the conference.
The MIPI sessions will include two “Board Level Hardware Engineering” education tracks on March 14, one dedicated to the MIPI I3C® utility and control bus interface, and the other focused on MIPI A-PHY® and the MIPI Automotive SerDes Solutions (MASS℠) framework. Other sessions will cover MIPI Camera Serial Interface 2 (MIPI CSI-2®), display specifications and various design considerations around MIPI interfaces.
The following sessions can be found on the embedded world program:
Session 5.2 - MIPI I3C (March 14)
All About MIPI I3C: The Next-Generation Utility and Control Bus
Michele Scarlatella, MIPI IoT Technical Consultant
As a sound replacement for numerous legacy serial buses such as I2C, SPI and UART, MIPI I3C provides a scalable, two-wire utility and control bus interface that can integrate a vast array of peripheral devices and sensors with microcontrollers and application processors. Originally introduced in 2016, MIPI I3C and the publicly available I3C Basic℠ version (released in 2018) support a number of innovative features that improve cost efficiencies and streamline integration.
This presentation will highlight the latest features added to the MIPI I3C and I3C Basic specifications, including the use of extra bus lanes to increase the interface speed to nearly 100 MHz, two additional High Data Rate (HDR) modes for better efficiency and reliability, group addressing and device-to-device tunneling. The discussion will also provide an overview of the significant resources available within the I3C ecosystem to aid developers, such as the host controller interface, addition of an I3C driver to the Linux kernel and several app notes, FAQs and white papers.
Advantages of MIPI I3C Enabling Simpler Design in a Variety of End Equipment Applications
Saminah Chaudhry, Texas Instruments
I2C and SPI have long been the primary interface choices for embedded devices. While these interfaces are relatively simple to implement and have been widely adopted over the years, they lack some critical features and have limitations. As smartphones, wearables, IoT devices, automobiles systems and server environments become more advanced and complex, the necessity for more streamlined, high performance, scalable and cost-effective communication interfaces are required to control and transmit data with high speeds, in energy- and space-saving designs.
So what is I3C and what is its goal? I3C aims both to fix the limitations of legacy interfaces and add significant enhancements. MIPI I3C is an intelligent multi-featured interface that improves upon key attributes of traditional I2C and SPI interfaces to provide a new, unified, cost effective and high-performing solution.
What are the main advantages of I3C? Is it backward compatible with I2C? What are the key applications of I3C beyond sensor integration? This presentation will dive deeper into system-level applications that use I3C for higher bandwidth at very low power levels, allowing for simpler, more flexible design implementation with features like target resets, In-band Interrupts, dynamic addressing and hot-join capabilities. The presentation will provide a thorough understanding of the key I3C features that allow easy adoption of the specification in a variety of use cases and end equipment applications.
An Efficient Prototyping Framework for I3C Controllers
Aradhana Kumari, STMicroelectronics
This presentation will cover a proposed highly robust, portable and low-cost test setup for at-speed validation for low- to medium-speed serial links and how it was successfully demonstrated for an I3C target device.
A complete I3C target controller softcore was developed in VHDL, and a pre-tapeout validation platform was built to exhaustively test the same. The validation objective also included verifying the interoperability of the developed I3C target with contemporary third-party controllers in a single-device and multiple-device environment. Further, the framework enabled the I3C target to be verified against a comprehensive set of real-time Conformance Test Suite (CTS) defined by the MIPI I3C standard.
There were multiple considerations while devising the low-cost, compact framework. Those included rapid programmability and fast debugging, a simple physical IO interface, multiple voltage domain options, bidirectional IO support, external push-button switches and an embedded logic analyzer. As some of the considerations are antagonistic for a single system, a new system was proposed and put together to effectively address them all.
Exhaustive tests were successfully conducted with the developed I3C target prototype, at different bus voltages and with multiple third-party I3C controllers and protocol analyzers. Although the proposed framework was designed for prototyping the I3C target controller, it can be extended to validate designs deploying any uni/bi-directional serial interfaces.
Session 5.3 - MIPI Automotive (March 14)
MIPI A-PHY: What’s New and What’s Next for the Automotive SerDes Interface
Edo Cohen, Valens Semiconductor, and Raj Kumar Nagpal, Synopsys, co-chairs of MIPI A-PHY Working Group
Since its introduction in 2020, the automotive industry’s first standardized asymmetric SerDes interface, MIPI A-PHY (also IEEE 2977), has undergone rapid development to meet evolving requirements and emerging architectures brought on by the increased use of sensor-based safety-critical applications and more immersive IVI in digital cockpits.
This presentation will focus on recent enhancements to A-PHY, as well as offer a preview of new features under development, including doubling the downlink throughput data rate to 32 Gbps per single lane while significantly boosting the uplink throughput to 1.66 Gbps. Other topics to be highlighted include the suitability of A-PHY for use in zonal architectures, new A-PHY protocol adaptation layers for additional configuration options, introduction of support for new power classes, expansion of the A-PHY ecosystem and plans for interoperability testing.
MIPI Automotive SerDes Solutions: Using a Standards-Based Approach for Functional Safety and Security Protection of Automotive Sensor Systems
Ariel Lasry, Qualcomm, and vice chair, MIPI A-PHY Working Group
As vehicles are outfitted with more sensor-based safety-critical systems, a standards-based approach to sensor connectivity can streamline integration and reduce complexity. These benefits can be further compounded if functional safety and security requirements have already been built into that solution.
This presentation will focus on how the MIPI Automotive SerDes Solutions (MASS) framework provides such an approach for connecting automotive sensors and displays to their associated ECUs, with built-in functional safety and security support. Topics covered include an overview of the framework’s components, as well as the functional safety features that have been embedded throughout the camera and display stacks. Also highlighted will be the framework’s end-to-end, application-based security approach, and discussion of how this overall solution will ultimately allow developers to embed functional safety natively at the "edge" – within the sensor and ECU components themselves.
How To Overcome Cable Length Limitations in MIPI CSI-2 Based Systems
Sebastian Guenther, Allied Vision
Many different applications can be solved by running computer vision algorithms on an embedded vision system. Those systems benefit from small weight and size, low power consumption and minimal hardware costs. The needed image data is often acquired by MIPI CSI-2 sensors and processed by highly effective SoCs. By leveraging the integrated image pipeline, the data can be transferred with low latency and high data rates into a system’s memory, without any interaction of the CPU.
In addition to those appealing characteristics, CSI-2 is well-supported by a wide range of different SoCs and integrated in many varied systems already. On the other hand, there are applications for which CSI-2 is not suitable, due to its restriction in cable length. The alternative camera interfaces often cannot compete with the benefits outlined above or come with much higher system costs. However, the FPD-Link from Texas Instruments and GMSL from Maxim Integrated offer interesting solutions to overcome this dilemma. Both represent physical layer standards, where data can be transmitted transparently to the user via coax or shielded twisted pair cables by using integrated SerDes technology. These solutions demonstrate that it’s possible to utilize the advantages of the MIPI CSI-2 interface to transfer image data over long distances, and keep system costs at a relatively low level.
Additional MIPI Presentations
Applications of MIPI UPLS Mode in Client Computing to Save System Power
Satheesh Chellappan, Lattice Semiconductor
March 14, 12:00-12:30
MIPI ULPS mode has been defined in MIPI D-PHY℠ standards for many years now, but adoption has been limited by ecosystem enablement and compelling applications. Camera sensor vendors have not been pushing the MIPI ULPS support in mainstream camera sensors for lack of use bySoC vendors. With the evolution of AI in computer vision, the streaming model is more adaptive and needs a sustained power-saving option, compared with the race-to-halt strategy of the past.
This presentation shows the application of MIPI ULPS mode in client compute systems, during modern connected standby and in active S0 system states. An end-to-end system architecture will be shown to explain the system flow for these applications. A power estimate analysis will also be shown compared with a legacy LP-11 state.
Using Smarter Interfaces for Edge Computing in Machine-Vision Applications
Haran Thanigasalam, MIPI Camera and Imaging Technical Consultant
March 16, 16:30-17:00
As machine-vision applications continue to evolve, there’s a growing need for smarter interfaces that connect multiple image sensors for near real-time perception and decision-making. By taking advantage of new specialized features in standardized interfaces, system architects can help offset centralized processing load, lower cost and power consumption, and simplify integration complexity.
The latest versions of the widely implemented MIPI CSI-2 interface have introduced features specifically to support these trends in machine-vision applications. Version 3.0’s Smart Region of Interest and v4.0’s Always-On Sentinel Conduit, Multi Pixel Compression, and RAW-28 capture features, for instance, enable sophistical machine awareness while reducing both system power and processing needs, making them well-suited for consumer, commercial and infrastructure platforms.
This presentation will provide a primer into MIPI CSI-2 and take a deep dive into how these new CSI-2 features and capabilities may benefit a broad range of image system platforms.
Using a Standards-Based Framework to Meet the Growing Bandwidth and Safety Requirements of Next-Generation Automotive Displays
(presented at the concurrent Electronic Displays Conference)
Ariel Lasry, Qualcomm, vice chair of the MIPI A-PHY Working Group
March 16, 11:00-11:20
As ADAS and autonomous driving systems have introduced more cameras and sensors, generating richer streams of display data, the move to digital cockpits has further compounded the challenge by adding even more display data streams, necessitating even greater bandwidth and, in some cases, the need for content protection. In response, the interfaces that connect these displays must offer higher bandwidth, low latency and functional safety.
This presentation will provide an overview of the MASS "display stack" of specifications that standardize and streamline connectivity of displays to their associated ECUs, with built-in functional safety and security support. The discussion will describe the components of the framework, including the MIPI A-PHY asymmetric SerDes interface, with particular emphasis on the framework’s functional safety features and flexibility in supporting multiple topologies and heterogeneous MIPI and VESA displays.
Connecting at the Event
MIPI Alliance extends its appreciation to all of these speakers for their participation in and support of this event. To meet with MIPI Alliance at the embedded world Conference, please contact Peter Lefkin, MIPI Alliance executive director, or Sharmion Kerley, MIPI Alliance director of marketing and membership.
Learn more about the embedded world event »