Jonathan Georgino, co-vice chair of the MIPI I3C Working Group and founder of Binho LLC
MIPI I3C® and its publicly available subset, I3C Basic™, which bundles the features most commonly needed by developers, bring unparalleled design advantages compared with legacy serial communication interfaces. Over the past couple years, we’ve seen significant traction from companies implementing I3C for a variety of use cases because it offers a substantial leap in performance and power efficiency. I’ll share some of those implementations, but first it’s useful to discuss how and why I3C is becoming the flexible utility and control bus interface of choice for system developers.
Evolution of the Interface
Like many MIPI specifications, MIPI I3C was developed to meet the high-bandwidth performance, low power consumption and low electromagnetic interference (EMI) requirements that embedded systems developers need in their mobile devices and other product designs. I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a unified, high-performing, very-low-power solution, delivering a robust upgrade path for I2C, SPI and UART implementations. Plus, it’s designed so legacy I2C devices can co-exist on the same bus.
A valuable tool in a developer’s toolbox, MIPI I3C provides a low-cost, off-the-shelf standardized bus solution with a small printed circuit board (PCB) footprint and an expanding ecosystem of peripherals, sensors and applications.
Since 2016, the interface has evolved, from the significant enhancements made to I3C v1.1 in 2019, to the most recent updates in I3C and I3C Basic v1.2, which reorganizes the specification into separate sections for mandatory and optional features that can be implemented based on application needs. This is great news for non-member implementers, as there is no difference between I3C and I3C Basic when it comes to required features and baseline elements.
My own journey with I3C started as a passion project, as a non-member implementer who developed a protocol analyzer for MIPI I3C to facilitate development of I3C-enabled hardware. Fast forward to today—my company makes I3C development tools currently used by 175+ different teams implementing I3C in their products; provides bespoke support, advising and contract development of I3C-capable devices; and I serve as co-vice chair of the MIPI I3C Working Group.
This gives me a unique view of the entire I3C ecosystem—from the engineers at semiconductor teams implementing I3C, to the technical sales and marketing teams selling them, and the embedded engineers implementing them in consumer products—and it’s exciting to see not only the growing set of products, applications and tools, but the increasing awareness, education and available resources for developers.
The Growing Ecosystem
When I think about what’s changed in the past couple of years that contributes to the growing list of companies and applications embracing I3C, much of the adoption can be attributed to increased awareness and knowledge of the interface.
One of the first mainstream use cases for I3C involved temperature management of DDR5 DIMMs, a key component in next-generation computing. Until recently, temperature management in DIMMs had been over I2C, which provides temperature data more slowly; and in turn, chip performance must be managed conservatively because the chips can’t be pushed to their maximum speeds due to the risk of overheating while waiting for updated temperature data. Because I3C provides temperature data more frequently, implementers can manage memory performance more aggressively. So when I3C Basic was adopted by JEDEC in its sideband bus and DDR5 standard, companies started rapidly integrating I3C into their temperature sensors, pushing it toward mass adoption for this use case–especially good timing to keep up with the explosive growth of data centers.
Use cases have expanded beyond temperature sensing applications for memory management. Companies are already integrating I3C for sideband management on solid-state drives (SSDs) and in applications employing MIPI Camera Control Interface (CCI). As product teams and engineers learn that this interface is an available IP block or peripheral in their companies’ catalogs, or they learn it’s implemented on the microcontrollers with which they’re working, they begin applying it in new applications and industries. MIPI I3C Basic has also been adopted by PCI-SIG and NVM Express as a modern alternative to the aging system management bus (SMBus) implementation for MCTP protocol transmissions.
In addition, the I3C interface is making its way into AR/VR applications such as smart glasses and AI-enabled wearable devices. This is a great fit because I3C offers a low pin count, best-in-class power efficiency and built-in capabilities that facilitate sensor fusion features like time stamping and the ability to get data from multiple sensors at the same time.
More recently, I3C has proven to be effective for streaming low-resolution sub-VGA grayscale images within a meager power budget (where MIPI CSI-2® is better suited for high-performance applications, including 1080p, 4K, 8K and beyond video, and high-resolution photography). For example, surveillance doorbell cameras are battery-operated with stringent low-energy requirements. The grayscale images are sufficient to do AI-based people or event detection, starting a full-resolution stream using CSI-2 when needed. In this example, MIPI I3C is an ideal companion to the more classic high-bandwidth video streaming protocols to enable new functionality previously unachievable by small form-factor battery-powered devices.
Other use cases include:
- Connecting inertial sensors, environmental/pressure sensors and other peripheral devices to processors in mobile and embedded systems.
- System debug and trace, described in the MIPI Debug over I3C specification
Resources, Support and More to Come
To support developers, MIPI has added specifications to facilitate the integration of MIPI I3C, including a Discovery and Configuration specification (MIPI DisCo for I3C™), an I3C Host Controller Interface (MIPI I3C HCI™), and a Transfer Command Response Interface (MIPI I3C TCRI™), all publicly available. Also, an I3C HCI driver is available in the Linux kernel.
In addition, the I3C FAQs, conformance test suite and several application notes are being updated to correspond with I3C/I3C Basic v1.2 and will be available soon on the I3C webpage. A MIPI I3C/I3C Basic Plugfest recently took place June 23-24, 2025, in Warsaw, where implementers of MIPI I3C, I3C Basic and I3C HCI had the opportunity to engage in interoperability testing between controller and target devices. And recently, MIPI’s new IO Bridges Working Group has begun work on the development of IOs over I3C bridge specification that should be complete next year.
As I mentioned earlier, working with I3C began as a passion project and now it has formed the foundation of my company's engineering tools and services. The more I work with it, the more possibilities I see. I highly encourage developers to familiarize themselves with the key features of I3C by downloading the specification, consuming the supporting literature such as the FAQs and listening to the MIPI webinar series, or even by conducting a hands-on discovery. It’s never been easier to get up and running with I3C by following the application notes and example projects from leading implementers. I’m certain you'll see many potential opportunities as well.