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A host controller interface for efficiently accessing MIPI I3C devices and capabilities


The MIPI I3C Host Controller Interface (MIPI I3C HCI) specification defines an interface that operating systems use to access MIPI I3C® devices and capabilities.

MIPI I3C HCI delivers crucially needed efficiency for designers of smartphones, computers, Internet of Things (IoT) devices, automotive systems and other applications that leverage the scalable, low-power, medium-speed, two-wire I3C utility and control bus interface. This specification provides application processor vendors with a consistent method for interfacing to MIPI I3C, eliminating the need for product-specific I3C drivers, helping to control cost and complexity, and freeing designers to focus their efforts on developing applications rather than interfaces.


For the latest version, MIPI I3C HCI v1.2, new optional features were added, including Scheduled Commands and Secondary Controller, Dead Bus Recovery and new register ALT_QUEUE_SIZE for Alternate Response Queue size in PIO Mode.

Additionally, this specification repurposes bit 28 in the IBI Status Descriptor and Broadcast CCC payload data from the Active Controller on the I3C Bus when the Host Controller is in Standby Controller mode and receives certain Broadcast CCCs. The specification also addresses memory partitioning in the case where the Host Controller supports both the DAT and DCT in Device Context memory.

Key features of the specification include:

  • Support for MIPI I3C primary controller operation on the I3C bus
  • Two modes of operation: programmable input/output (PIO) mode, delivering direct data interface support with programmable buffer depths for the transmit/response and data buffer, and direct memory access (DMA) mode, providing interface support for scatter gather transfers for data buffers
  • Power-efficient operation of the host controller, which helps maximize battery life in mobile devices
  • Support for I3C data rates, including I2C fast mode (up to 400Kbps), I2C fast mode+ (up to 1Mbps), I3C SDR (up to 12.5Mbps) and optional I3C HDR Modes (for faster transfers)
  • Support for extended capabilities, including vendor-specific ones, to enable more sophisticated hardware or additional functionality
  • Group addressing, which enables multicast-type addresses to be assigned to multiple peripheral devices
  • Defining bytes for common command codes (CCCs), extending greater flexibility to create additional CCCs or augment the existing CCCs defined in I3C
  • Scatter gather for ring pointer, flow control, PIO/DMA mode indicator, ring full indication and other features for improved performance in DMA mode

The previous public versions (v1.0 and v1.1) are available upon request.

MIPI Alliance welcomes contributions to the specification. If you would like to contribute, please contact the MIPI Software Working Group at

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