MIPI Low Latency Interface

MIPI Low Latency Interface, MIPI LLI^SM, provides a point-to-point interface between the application processor and modem/baseband processor. It enables the baseband processor to access the application processor’s dedicated DRAM memory for baseband processor operations, eliminating the need for the baseband processor to have its own dedicated DRAM chip. The interface reduces pin count, saves board space and reduces the bill of materials for a device. Elimination of a discrete chip also helps reduce system-level testing for OEMs to shorten design cycles and expedite time to market.

MIPI LLI uses the MIPI M-PHY physical layer. The MIPI LLI stack also provides a PHY adapter, data link layer and transaction layer. The interface also allows for sideband signals between the two chips to further improve overall system communication. Operation on MIPI M-PHY can reduce system power by leveraging the MIPI M-PHY sleep and hibernation power modes. MIPI M-PHY can also scale data throughput. The connections employ memory-mapped transactions for communications via native protocols such as Open Core Protocol and Advanced Microcontroller Bus Architecture.

MIPI LLI is developed by the MIPI Low Latency Interface Working Group.

Note: The full specification is available only to MIPI Alliance members. For information about joining MIPI Alliance, visit Join MIPI.