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            4 min read

            Coming Up - MIPI Sessions at embedded world Nuremberg 2026

            Picture of MIPI Alliance MIPI Alliance : 10 May, 2025

            MIPI A-PHY MIPI SWI3S MIPI I3C
            Featured Image
             
            10-12 March 2026
            Nuremberg, Germany
             

            The 24th edition of the embedded world Exhibition & Conference will take place 10-12 March 2026, in Nuremberg, Germany. This premier event for the embedded systems industry connects researchers, developers, industry and academia from all disciplines of the embedded world. MIPI Alliance serves as a community partner for the event.

            The upcoming conference will include presentations featuring MIPI I3C®, the recently released MIPI SWI3S™ and MIPI A-PHY®, during three sessions focused on hardware design, use cases for medical applications, and architectural design. Read more below about the presentations, and use the MIPI code "ewC26CPK" to receive a 15% discount on registration.

             

            Register for the Conference

             

            Session 4.3: Hardware Design - MIPI Interfaces

            10 March | 4-5:30 p.m.
            10 March | 4-4:30 p.m.

            MIPI I3C Serial Bus: Latest Features and Market Applications

            Michele Scarlatella, MIPI Alliance

            MIPI I3C® is a versatile, two-wire serial bus designed to connect peripherals to microcontrollers with high efficiency. The past year has seen a surge in products that are I3C-capable; and during this period, MIPI has also released v1.2 of the specification and a multitude of supporting developer resources.

            The initial part of the presentation will provide engineers and developers with an introduction to the MIPI I3C interface, covering key features that differentiate I3C from I2C, and an overview of some more advanced features such as high data rate modes, multiline coding and target reset. This part will also highlight the improvements introduced in the latest I3C v1.2 release, and newly released developer resources.

            The second part of the presentation will introduce the latest developments within the I3C ecosystem, explaining how new applications are using I3C to overcome challenges associated with using legacy I2C, SPI and UART interfaces. Application examples will include use of I3C as a system management bus for DDR5 memory modules, I3C as a sideband bus for SSDs, I3C as debug interface, and more.

            The presentation will conclude with a brief description of the key new features MIPI is planning to address in the next release of the I3C interface specification.

            10 March | 4:30-5 p.m.

            Turning Up the Volume: How SoundWire I3S Transforms Embedded Audio

            Ettore Antonino Giliberti, SmartDV Technologies

            MIPI SoundWire I3S (MIPI SWI3S™), the evolution of the original MIPI SoundWire® protocol, enables efficient audio, control and power management in integrated, low-latency and power-sensitive systems. Unlike legacy SoundWire, where devices are independently discovered and controlled, SWI3S groups multiple audio devices under a single logical entity, presenting multiple endpoints as one integrated system. This simplifies system management and synchronization, making it ideal for next-generation laptops, tablets and AI voice assistants.

            SWI3S improves upon its predecessor with higher bandwidth for a similar link size by removing direct peripheral-to-peripheral communication in the control stream and offering flexible allocation to manage multiple audio transmitters or streams. An optional DLV PHY layer with differential low-voltage signaling supports longer links and enhances EMI/EMC performance, crucial for designs with microphones near RF antennas. The protocol also supports higher data transfer rates and detailed standby/wakeup modes.

            From a design perspective, adopting SWI3S requires updates to manager and client implementations to handle device grouping, increased bandwidth and enhanced protocol capabilities. This article presents a real-world system example, illustrating system-level architecture and implementation challenges compared to legacy SoundWire.

            10 March | 5-5:30 p.m.

            Wire for Intelligence: SWI3S The New Sensor Interface for Ambient AI

            Manuela Heiss, Infineon Technologies AG

            As voice becomes the natural interface for AI systems, especially in wearables and edge devices, the limitations of legacy audio protocols like PDM are increasingly exposed. These older standards lack the scalability, synchronization and embedded control required for intelligent, multi-microphone architectures.

            Enter MIPI SoundWire I3S (MIPI SWI3S™)—the next-generation interface standard designed to meet the demands of ambient AI. With support for up to 12 peripherals on a single 2-wire bus, dynamic scheduling, and integrated control signaling, SWI3S enables compact, power-efficient microphone arrays that are purpose-built for voice-first interaction.

            This presentation will explore how MIPI SWI3S is already unlocking new possibilities in smart glasses, where products like Meta Ray-Ban and Oakley frames integrate 5+ microphones per unit. These wearables represent a shift toward seamless, conversational AI—where synchronized audio capture and reduced wiring complexity are no longer optional, but foundational.

            By aligning MEMS innovation with the rise of ambient intelligence, SWI3S is not just a technical upgrade—it’s the new interface standard for AI communication.

             

            Session 8.1: Use Cases for Embedded - Medical Applications

            11 March | 10:30-11 a.m.
            11 March | 10:30-11 a.m.

            Confronting the Connectivity Challenge in Endoscopic and Robotic Surgeries

            Effi Goldstein, Valens Semiconductor

            Modern surgeries include higher resolution imaging systems, endeavoring to give surgeons the best possible view of their patients. 3D imaging, for example, requires multiple high-resolution cameras and sensors for capturing various angles and an accurate stereoscopic view. This trend introduces significant challenges, including increased bandwidth demands, space constraints within robotic arms and endoscopies, and the need for ultra-reliable, zero-latency connectivity.

            The success of these modern surgical implementations hinges on reliable, high-speed connectivity between the various components. Any video delay or data loss during surgery can compromise surgical accuracy and lead to irreversible errors – making latency and data loss potentially life-threatening.

            A major barrier for reaching higher resolutions in robotic and endoscopic surgeries has been the lack of connectivity solutions that can maintain signal integrity despite electrosurgical interferences. This presentation will discuss how the industry is evolving to more compact, high-performance robotic and endoscopic systems, such as the MIPI A-PHY® standard for high-speed connectivity. Broader adoption of such technologies may support the next generation of surgeries, from robotic to single-use endoscopic.

             

            Session 4.6: Hardware Design - Architectural Design

            11 March | 3:30-4 p.m.
            11 March | 3:30-4 p.m.

            MIPI A-PHY as an Enabler for Remote Multi-Head “Smart Camera” Architecture 

            Jonathan Regalado-Hawkey, Valens Semiconductor

            Today’s smart cameras are big, expensive and can be complicated to install. They rely on multiple thick cables – one for data, one for control, one for power – which drives up the cost and maintenance, while they typically don’t support sensor fusion either. Furthermore, due to their size, they can present a challenge when installed in physical restrictive locations.

            MIPI A-PHY®-based remote-head architecture could help the industry transition to a smaller remote-head architecture. The remote camera head can connect to a processor ("smart box") over a thin cable that carries uncompressed (raw) video, control signals and power. This enables for much smaller, lower-cost, low-power cameras, simplifies cabling and improves reliability. The A-PHY-based solution also delivers high EMC resilience, always-on diagnostics, precise multi-camera synchronization, and native support for sensor fusion – reliably supporting multiple cameras connected to a single AI processor.

            This presentation will review how MIPI A-PHY achieves the remote camera and multi-head architecture, comparing the A-PHY-based solution to proprietary options like GMSL3 and FPD-Link IV. It will also include a review of the benefits of A-PHY in traditional embedded systems.