The SPMI specification is optimized for the real time control of any device requiring control connectivity such as power management ICs. The SPMI shared bus is scalable from simple to complex architectures with the following features:

• Low pin count and low gate count

• High speed compared to legacy interfaces

• Low latency

• Supports multiple processor devices using the same shared bus

• Priority management by traffic classes

• Command acknowledgement supported in SPMI v2.0

The SPMI specification including the Protocol Implementation Conformance Statement (PICS) and a Frequently Asked Questions (FAQ) document are available to MIPI members only.

For more information on joining MIPI, please go to Join MIPI.

Introduction

The complexity and performance requirements of portable electronic devices are increasing at an ever-accelerating rate. As the demand increases for new high performance features, system level power management is more critical. The use of advanced power management techniques to reduce power consumption and improve battery life is becoming more important than ever before for portable devices such as wireless handsets, tablets, handheld gaming consoles and portable media players. 

To minimize power consumption in portable electronic devices, system and IC designers are now using advanced power management techniques to:

• Accurately monitor and control processor performance levels required for a given workload or application
• Real-time, dynamic control of various supply voltages based on the performance levels

The System Power Management Interface (SPMI) specification standardizes the hardware interface between baseband/application processors and peripheral components to support such advanced power management techniques.  SPMI reduces time-to-market and design costs of mobile terminals by simplifying the interconnection of products from different manufacturers.

Scope

The SPMI specification describes the low-level protocol, communication sequences and arbitration processes of the interface. The hardware bus topology, I/O structures/physical layer and signal timing requirements are also described. Higher level protocols, software driver design and implementation-specific details are out of scope of this document.