Snapshot of MIPI RFFE v3.0 from a System-Architecture Perspective
Lalan Mishra, Vice-chair, MIPI RFFE Working Group
Since its release in July 2010, the MIPI RFFE℠ specification has evolved as the de-facto multi-drop bus architecture to control RF Front-End components. Over the past decade, its constant evolution has ensured absolute adherence to real-time performance of the RF-Front-End in terms of the critical control timing budget. As the latest cellular technology (5G) takes the RF-Front-End to a whole new level of complexity, the recently released MIPI RFFE v3.0 is geared toward meeting these new challenges.
This session presents the new features of MIPI RFFE v3.0 from a system-architecture perspective to help architecture and design engineers understand how the triggering features in the latest version work together to improve performance and to switch quickly among the various bands and band combinations in a 5G system:
- Timed triggers that allow for tighter, synchronized timing control of multiple carrier aggregation configurations
- Mappable triggers that enable groups of control functions to be remapped
- Extended triggers that boost the number of unique triggers available in the RF control system and accommodate increasingly complex radio architectures
Lalan Mishra is currently employed with Qualcomm Inc. as principal engineer, and in his current role, he focuses on conceiving next-generation chipset connectivity architecture involving digital and RF circuits. Active at MIPI since 2012, Lalan chairs and co-chairs the Reduced Input-Output (RIO) and the RFFE workgroups respectively. Lalan has 143 patents (issued) and 187 patents (pending) to his credit. He holds a master’s degree from UCSD with specialization in wireless embedded systems.