Conference Hours: 8:30 AM - 5:45 PM
Exhibit Hours: 12:15 - 1:15 PM, 2:45 - 5:45 PM
Abstract: The MIPI I3C bus is an intelligent serial interface, with flexible bus management architecture. It aims at enhancing the benefits of speed and energy efficiency of the data transfer by adding several features that streamline various type of transactions. In addition, those features are designed to facilitate the System Design, providing scalable and efficient interconnectivity solutions. The System Designers challenges and their wish-lists were taken in consideration, materializing into the comprehensive list of I3C features. The Flow Control and the Timing Control tools provided by MIPI I3C interface are the subject of this presentation. Elements of solved problems, their challenges and practical aspects are included.
Radu Pitigoi-Aron is a System Architect at Sensors Advanced Technology Group of Qualcomm Technologies, Inc. Radu works on next generation of Mobile and Internet Devices, empowered by the intelligent use of information gathered from sensors, traditional and ground breaking. He is Contributor to MIPI I3C Interface and has been presented with the Specification Award for his work on Version 1.0. Before joining Qualcomm, Radu held several Lead Project positions, across three continents, in Romania, South Africa and lately in USA. He has covered a wide spectrum, including classical Analog design, real-time digital/analog embedded systems, intelligent lighting controllers, system architecture. He received a M.S. in Electronics Engineering from Polytechnic Institute of Bucharest, Romania. Radu is the holder of 23 USA Patents on Electronics topics.
Abstract: The three high-speed serial standards namely - MIPI D-PHY, MIPI M-PHY and MIPI C-PHY, although having similarities in terms of target segment and application use cases, do have wide contrasts with respect to electrical specifications. MIPI D-PHY is a forwarded clock system, MIPI M-PHY has maximum toggle rate of up to ~12Gbps and MIPI C-PHY is 3-level 3-wire signal. Inevitably, engineers will encounter varied issue/challenges while debugging or testing these designs. This presentation shall provide real world problems faced and the process of uncovering them early on using the test and measurement equipment & solutions. The solution could be in terms of measurement & analysis of signal characteristics, probing with fidelity and waveform generation with precision. In addition, this session shall highlight the test solutions you will need to support the upcoming revisions of these MIPI PHY specifications.
Ramesh from the past 20+ is working on developing compliance measurements for various technology like HDMI, MHL, Ethernet and MIPI . He also contributes to Standards specifications and test methodologies of many high speed serial technologies. Apart from measurement development, he also involved in solving the customer issues relating to Test and measurement and also instrumental in developing the system level solution for Testing. He holds 5 US patents for various T & M functionalities/procedures.
Parthasarathy, Chair of the MIPI Test Working group at MIPI Alliance, is a System Engineer for MIPI technology segment at Tektronix. He is involved for the past 9 years working on signal generation solutions for waveform generators & measurement solutions for real-time oscilloscopes. His current focus is on test solutions for MIPI High Speed PHY Technologies. He holds a US patent for a method to emulate crosstalk. Prior to joining Tektronix, Partha was involved with embedded device drivers for mobile platforms and has designed algorithms for wide range of DSP solutions.
Abstract: Preparing to implement MIPI’s new sensor interface, MIPI I3C, in your next design? Curious about MIPI I3C's proliferation beyond basic sensing? This presentation will provide adopters of MIPI I3C with targeted guidance on how to ensure a successful and efficient implementation of I3C in their mobile and mobile-influenced products. Leveraging I2C as a foundation, many components of I3C will be familiar to implementers, but with guidance provided here, attendees will leave with a clearer understanding of I3C’s key innovative features, how they will improve their systems and what considerations should be made to fully leverage them. Implementation guidance will include, but not be limited to support for legacy I2C devices, understanding network topology tradeoffs and good design practices.
Ken Foust, Intel Corporation is a Sensor Technologist and Researcher who leads sensing initiatives across Intel’s product portfolio and R&D labs. He is also the Chair of the MIPI Sensor Working Group. Previously, Ken was a Director at Kionix, Inc., started his career at IBM and received a BSEE from Alfred University.
Abstract: BitifEye demonstrates how to enable Physical Layer testing with help from the Protocol Layer. In particular we focus on MIPI UniPro and UFS devices, which can be easily tested through the UniPro Test Mode. It allows in-band link configuration as well as frame and error counter retrieval, standardizing the test setup and removing the need for out-of-band connections to the DUT. This reduces setup and test time and provides the most complete and reliable solution to test the Physical Layer. Complementary to the presentation, our booth will feature a live demonstration of the solution, using a UFS 2.0 Device from SMI.
Victor Sanchez-Rico is the Project Manager for the MIPI test software at BitifEye, Keysight’s Solutions Partner for high speed interfaces. This Computer Science engineer is also a father of three and a sports cars aficionado. He will solve all your testing needs while proudly showing you pictures of his daughters on his MIPI-enabled smartphone.
Abstract: MIPI I3C enables multiple sensor connectivity using a single integrated bus with minimal pin count and throughput up to 33 Mbps. This presentation briefly describes I3C and its key features, and through examples details how I3C can be used in IoT and automotive systems to enable a more intelligent sensor connectivity. I3C provides lower cost, lower power and better scalability than I2C and other interfaces, making it ideal for sensor and non-sensor applications such as touch. Hear how you can integrate the unique benefits of I3C into SoCs and systems with compliant MIPI IP.
Sriram Balasubramania is a Director of R&D at Synopsys. He has more than 25 years of VLSI design experience with a focus on connectivity protocols. Mr. Balasubramanian’s primary interest and area of work are in products based on MIPI, JEDEC, USB and SD standards. Mr. Balasubramanian holds a BTech degree in Electronics and Communication Engineering from Calicut University India and an MBA from Indian Institute of Management, Bangalore.
Abstract: This presentation will review the features of MIPI M-PHY Gear 4 and their impact and implementation within UniPort/UFS Protocol. Teledyne LeCroy will discuss how UniPort and UFS will implement the higher speeds of Gear 4 and introduce the changes between UniPort Version 1.61 and Version 1.80. We will also present the changes from UFS 2.1 to UFS 3.0 and changes that should be noted in the Protocol between host and device.
Roy Chestnut is the Director of Technical Marketing for the Teledyne LeCroy Protocol Solutions Group. Roy has been with the Protocol Solutions Group for 16 years. Along with his responsibilities as Director of Technical Marketing, he also has principle responsibility for the Teledyne LeCroy PSG Mobile and DDR product lines. Roy has been a member of MIPI Alliance since 2008. He has over 30 years of experience supporting High Speed Serial Data and Networking Protocols. Roy has a BS degree in Business Administration-Information Systems Management from San Diego State University and over 35 years of experience supporting High Speed Serial Data and Networking Protocols.
Abstract: In a typical mobile influenced system a large number of sideband GPIOs are used which add to package size and cost. FSM based MIPI VGI aims to consolidate these sideband GPIOs and low speed messaging over a 2- or 3-wire interface. VGI FSM could also be used behind a suitable serial interface, such as I3C. MIPI VGI v1.0 spec is nearing its completion and is expected to be released next year.
Lalan Mishra has over 25 years of design and innovation experience in the field of Wireless Embedded Systems (Smartphones/Tablets/eBook etc.), Lalan is currently employed with Qualcomm Inc. as Principal Engineer - Advanced Connectivity Technology. In his current role, Lalan focuses on conceiving next-generation chipset connectivity architecture involving digital and RF circuits with the goal to minimize cost, power, latency and pin-count. Lalan conceived the idea of Virtual GPIO Interface (VGI) back in 2012 and this concept is now in the standardization process at MIPI under the umbrella of Reduced Input-Output Work-Group (RIO-WG), chaired by him. Lalan has 11 patents (issued) and 118 patents (pending) to his credit. He holds a Master’s degree from UCSD with specialization in Wireless Embedded Systems. In his spare time, he loves to dive into Natural Philosophy and plays classical ragas on Indian bamboo flute.
Satwant Singh is the Senior Director of Strategic Planning at Lattice Semiconductor, where he is responsible for ecosystem involvement for new developments and Lattice’s product capabilities roadmaps. Singh serves as the Vice Chair of MIPI Alliance’s RIO Working Group, as well as for the MIPI Sensor Working Group focused on developing new I3C interface specification. Singh holds a master’s of science in Electrical Engineering from the University of Toronto and has more than 30 patents.Satwant Singh is the Senior Director of Strategic Planning at Lattice Semiconductor, where he is responsible for ecosystem involvement for new developments and Lattice’s product capabilities roadmaps. Singh serves as the Vice Chair of MIPI Alliance’s RIO Working Group, as well as for the MIPI Sensor Working Group focused on developing new I3C interface specification. Singh holds a master’s of science in Electrical Engineering from the University of Toronto and has more than 30 patents.
Abstract: In the fast-growing mobile industry, there is a constant need of reducing the sizes of mobile chips, which is accomplished by reducing the number of pin connections in a chipset. SPMI protocol plays a vital role in doing so, as it supports multi-master and multi-slave systems. It is generally used to send transactions between the processor and the PMICs. There are occasions where the processor is in sleep, but the inter-PMIC communication exists. This motivation has led to the requirement of multiple SPMI masters – one on the processor and other on the PMIC. Since, the processor and the PMICs exist as different chips, there is a challenge to verify the multiple masters. A system-level test bench is required where both the masters are instantiated. The major verification efforts lie in validating the scenarios like multiple masters waking up at the same time and trying to connect, second master trying to connect when one master is already present, multiple masters and slaves arbitrating with different priority levels, BOM (Bus Owner Master) transfer, disconnection of a master using TBO (Transfer Bus Operation) or during hard reset or during command parity error, noise injection during various phases of a transaction and recovery after it, watchdog timer expiry and internal reset in the slave when SPMI clock is stopped abruptly during a transaction. Our paper elaborates on the multi-master multi-slave test bench and how the verification challenges were handled and closed.
Sanjeev Kumar has around 8+ years of industry experience in ASIC Design Verification and is working with Qualcomm as a Senior Lead Engineer. He has expertise in the verification of peripheral IPs (SPMI, PMIC Arbiter), Ethernet IPs (MAC, Port) and Point-of-Sale (PoS) IPs. He has extensively worked in constraint random verification using System Verilog and UVM-based verification environment. He has done B.E. from BITS-Pilani and his hobbies are traveling, playing cricket/badminton and watching movies/TV series.
Purva Joshi has around 4+ years of industry experience in ASIC Design Verification and is working with Qualcomm as an Engineer. She has experience in IP as well as SOC verification. She has expertise in formal verification. She holds a B.E. degree and her hobbies are playing badminton, gardening, watching movies.
Ritesh Jain has around 16+ years of experience and is working with Qualcomm as a Senior Staff Engineer/Manager. He has an extensive experience in IP/CPU/Multi processor/SOC verification. He champions in the field of low power verification and mixed signal verification. He is a pass out of BITS-Pilani and has hobby as Painting.
The MIPI Alliance has historically developed interface specifications primarily for the Mobile Handset Market. However, MIPI Interfaces are also finding use in Automotive applications where there is a desire to take advantage of low power, low EMI, high performance data links and the significant economies of scale that compatibility with Handset targeted interfaces can bring. Recently the MIPI Alliance has received requests from some Automotive OEM’s and Tier One suppliers to extend the current specification for the Camera to Processor “point-to-point” interfaces in several ways that meet Automotive requirements. A new Automotive sub-Group (AsG) has been formed and is now in the process of gathering requirements for implementing next generation high speed data communications links in Automobiles. This paper provides an overview of the activities and approach of this new Automotive group.
Matt Ronning is the Director of Engineering for Sony’s Component Solutions Business Division located in San Diego, California. He manages a small engineering team that provides both application & system engineering support for a diverse set of products, including: GPS, Bluetooth, Wireless Power, NFC, MMIC devices, Power Stages, etc. Previous Sony assignments have included managing Sony’s Automotive Camera business for North America and new business development, with a special focus on the automotive market. Currently Matt is the chair of the MIPI Alliance’s Automotive sub-Group, with the charter to extend MIPI Alliance’s specifications into the automotive market. Matt’s educational background includes an MSEE specializing in Communications Systems from Arizona State University and a BSEE from the California Institute of Technology.
Abstract: Day by Day we are moving through the process of MIPI Globalization in Mobile Industry by converting all the available interfaces (like camera, IPC and storage)to MIPI UniPort M based interface. Based on this point, even though silicon vendors are ready with MIPI controllers (i.e. DUT’s) its taking huge time to develop Host Platform for Validation of DUT. From this observation am coming up with a Reconfigurable Host for all UniPort-M based peripherals like Chip 2 Chip (i.e. IPC), Camera (i.e. CSI-3), Storage (i.e. UFS).By using this platform we can switch the host protocol on the fly between IPC , CSI-3 and UFS. The major advantage of designing this kind of host platform was to reduce the HW resource development time and cost. We have to use Xilinx Zynq FPGA as the processing module for building Reconfigurable Host. User will always have 3 different options to switch between different host protocols.
Sreekanth Varma Dantuluri has been a VLSI/FPGA Engineer at Western Digital since 2014. He received his master’s degree in VLSI from IIIT in 2008. He has been actively participating in MIPI discussion’s and working on MIPI-based solutions for the past 3 years. He is very energetic in debugging MIPI UniPro and MIPI M-PHY related issues.
Shiou Mei Huang is an Automotive Hardware Applications Engineer at Texas Instruments (TI), based in Sugar Land, Texas, USA. Shiou Mei obtained her bachelor’s degree in electrical engineering from SUNY Stony Brook University before joining TI in 2012. She is currently responsible for product characterization and applications support in the automotive realm. One of her key roles is to ensure automotive infotainment and ADAS customers can release product to market in a timely fashion.
Mayank Mangla is an Imaging Architect at Automotive Processors Business Unit of Texas Instruments, based out of Dallas, Texas, USA. He is passionate about Digital Image Processing, being involved in the field since 2001. In the last 16 years se has done some pioneering work in camera algorithms and applications. He holds several patents and has authored numerous papers. His current focus area of research is ADAS (Advanced Driver Assist Systems) imaging, involving automotive applications like Electronic Mirrors, Park Assist Systems, Autonomous Driving etc.
Abstract: MIPI has released new MIPI C-PHY, MIPI D-PHY and MIPI M-PHY specifications this year to address the next generation of the 5G mobile era to include VR (virtual reality), AR (augmented reality) and autonomous vehicle technology. Those new MIPI PHY specifications will bring new technology innovation that will also bring new challenges to design or evaluation engineering. In this session, we will look at the key changes in the specification and CTS (conformance test suite) and address the challenges to support the new PHY layer.
SK Choi is the Keysight Technologies Solution Expert and Product Manager for MIPI Alliance solutions. SK is currently a contributor to the MIPI PHY Working Group and member of the MIPI TSG (Technical Steering Group). He has completed 10 years working for Keysight. He has a bachelor’s degree in Electrical Engineering from Korea.
Abstract: Use of image sensors expanded beyond simple image capture to capture images in multiple angles, multiple exposures etc, which allows building more intelligence to systems used in Vision, Automotive, Industrial and other product segments.
MIPI specifications being mature, relatively simple to use and well proven in mobile segment, the ability to combine multiple camera data streams over a single CSI-2 channel, supporting long distance using bridge functions makes MIPI CSI-2 image sensors a best bet for the above said product segments.
The presentation details some of the multi-camera, long distance use case scenarios, the role and value addition of FPGA’s to implement these systems.
Kondalarao Polisetti is Senior Design Engineer at Xilinx with 11+ years of experience in IP solutions development for Xilinx FPGAs. His expertise include developing IP solutions for Embedded, Automotive, Medical and Radar segments. Some of the protocols/IP include CAN, MOST NIC, AXI Generators, Checkers, Performance monitors & MIPI Subsystems. Xilinx has been active MIPI member since 2014.
Abstract: Today mobile devices achieve new heights in data rates with every new device. Higher data rates lead to the problem of inter-symbol interference. To overcome this issue, designers can use equalization circuit at the receiver. Equalizer matches the impedance of transmission lines to reduce the inter-symbol interference. Most common equalizer used in digital communication is the adaptive equalizer, which uses training sequences to get the required coefficient settings. The latest MIPI PHY specifications (M-PHY, D-PHY and C-PHY) introduce training sequences for the equalizer settings to reduce inter-symbol interference: adapt sequence in M-PHY, alternate sequence in D-PHY and C-PHY. In addition, C-PHY uses preamble and user-define sequences. This paper describes various training sequences used in MIPI PHYs to reduce inter-symbol interference.
Manoj Sharma Tanikella is working as Sr. R&D Engineer at Synopsys India Pvt. Ltd. Responsible for designing Verification IPs as part of Verification Group at Synopsys. He urrently is involved in verification IP development of JEDEC UFS and MIPI portfolios like MIPI M-PHY, MIPI D-PHY, MIPI C-PHY, MIPI CSI-2, MIPI DSI and MIPI UniPro.
Amitkumar Shrichand Gound is working as Sr. R&D Engineer at Synopsys India Pvt. Ltd. Amit is responsible for designing Verification IPs as part of Verification Group at Synopsys. He currently is involved in verification IP development of MIPI portfolios like MIPI M-PHY, MIPI D-PHY, MIPI C-PHY, MIPI CSI-2, MIPI DSI and MIPI UniPro.
Abstract: The drive for high resolution embedded displays is increasing in applications such as mobile, automotive and augmented/virtual reality (AR/VR). Automotive infotainment and display-based advanced driver assistance systems (ADAS) are more sophisticated and require high-resolution displays to mimic high-end mobile-quality user experience. For AR/VR, high frame rates and multiple display architectures are deployed to meet the unique characteristics of these applications such as avoiding motion sickness and eye-glass form factor. Due to increase in display quality and resolution, it is critical for designers to access solutions with more efficient processors and interfaces that support high-performance, low data-transmission bandwidth and low-power consumption. This presentation describes a display solution, co-developed by Synopsys and ARM, that improves visual quality and reduces overall SoC power consumption while meeting the requirements of 4K high-resolution embedded displays in new applications beyond mobile.
Hezi Saar is a Senior Staff Product Marketing Manager at Synopsys and is responsible for its DesignWare HDMI, Mobile Storage and MIPI IP product lines. In addition, he co-chairs the MIPI Alliance Marketing Steering Group and sits on the MIPI Alliance board of directors. He brings more than 20 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, Mr. Saar was responsible for Advanced Interface IP at Virage Logic, acquired by Synopsys in 2010. From 2004 to 2009, Saar served as senior product marketing manager leading Actel's Flash field-programmable-gate-array (FPGA) product lines. Previously, he worked as a product marketing manager at ISD/Winbond and as a senior design engineer at RAD Data Communications. Mr. Saar holds a Bachelor of Science degree from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.
Ashraf Takla is President and CEO of Mixel, Inc., which he founded in 1998. Before founding Mixel, he was Director of Mixed-Signal Design at Hitachi Micro Systems. Ashraf has 35 years of experience in analog and mixed signal design, and holds 5 patents.
C.K Lee is a Director of SERDES PHY design at Qualcomm Technologies, Inc. He has worked for Samsung and Enhanced Memory Systems before joining Qualcomm. C.K. has 27 years of experience in analog & mixed signal design.
Abstract: Mixed Reality promises to bring in the next wave of experiences to consumer and enterprise segments. Enabling this requires a combination of different types of image capture modalities from among RGB, Depth and Beyond Visible cameras with rolling/global shutters and different FOV requirements, both on a head mounted device and in the environment. This talk will tie the different usage opportunities to imaging requirements for a Mixed Reality system for both consumer and enterprise markets in the coming years and dive into system design aspects like placement, location, types of image sensors, bandwidth requirements for tethered and wireless HMD scenarios and the processing pipeline architecture with the critical technology building blocks from multiple camera sources distributed between a HMD and a host system. Example end usages like Obstacle Avoidance and Avatar Navigation with Mixed Reality headsets will be used to provide a use case decomposition view from capture to application. Finally, the talk will address some of the opportunities for the MIPI community to drive the next wave of experiences with advanced image capture modalities and the challenges to be addressed to achieve them.
Prasanna Krishnaswamy is a Platform Architect in the Client Computing Group at Intel. His expertise is on imaging and computer vision systems architecture, tying imaging system designs with algorithmic image processing and vision blocks on the SOC and platforms, to deliver end to end imaging and vision use cases for mobile and PC like form factors. At Intel, he has contributed to the development of platform imaging solutions in the areas of Depth Sensing and Array cameras. Prior to Intel, he was managing the software stack development at Aptina Imaging for their Image Signal Processor product line. Prasanna holds a Master’s Degree in Electrical Engineering from the University of Arizona and has more than ten patents granted or pending.
Abstract: As a sequel to our previous MIPI C-PHY introduction presentations, we start by briefly covering MIPI C-PHY basics and the latest enhancements in recent revisions of the specification. Subsequently, we delve into a description of innovations in the next generation MIPI CSI-2 and MIPI DSI-2 protocols that are made possible by quite elegant properties of the MIPI C-PHY encoding scheme and its associated MIPI Alliance specification innovations. For example, we illustrate concepts of low latency, expanded virtual channel and interleaving support for IoT applications, and compression schemes such as those used in 30-bit display implementations.
Dr. Mohamed Hafed is the Chief Executive Officer of Introspect Technology, a leading manufacturer of innovative test and measurement products for high-speed digital applications. A passionate technology speaker, Dr. Hafed contributes to the MIPI Alliance working groups, and he actively participates in MIPI technology promotion activities worldwide.
Abstract: SoundWire is a robust, scalable, low complexity, low power, low latency, two-pin (clock and data) multi-drop bus that allows for the transfer of multiple audio streams and embedded control/commands. SoundWire provides synchronization capabilities and supports both PCM and PDM, multichannel data, isochronous and asynchronous modes. It was ratified by MIPI in 2015. The Linux Subsystem for SoundWire is being upstreamed by presenters to Linux Kernel and we explore this new Subsystem. The SoundWire bus is explained in detail along with the core bus structures, Master(s) and Slave(s) interface (APIs, Structures) with bus and changes required by existing device drivers to add SoundWire support. We also explore the support for various architectures and underlying enumeration methods. This presentation would help people to get upto speed with this new Subsystem & protocol.
Sanyog Kale is a Software Development Engineer who works with Intel and has 7 years of industry experience. He has expertise in audio domain and has worked on Audio Firmware, Audio DSP engines, Linux Audio drivers to deliver best audio solutions for all the Intel platform(s) based on Android and chrome OSes. He is currently working on developing & upstreaming SoundWire (MIPI Standard) Linux subsystem which includes Bus framework, Master Driver and Slave driver.
Vinod Koul works in Linux Audio group for Intel. He is involved in Audio driver development and upstreaming for Intel platforms. He also wrote and maintains the ALSA compressed audio framework. Vinod is the maintainer of Linux DMA engine subsystem.
Abstract: MIPI D-PHY is the de-facto standard for camera and display connectivity using low-latency transitions between high-speed and low-power modes with high noise immunity and high jitter tolerance. This presentation briefly describes MIPI D-PHY’s flexibility, speed, power and cost benefits for cameras and displays in mobile applications. Today, automotive infotainment and advanced driver assistance systems (ADAS) such as image, radar and lidar are also taking advantage of MIPI D-PHY’s unique benefits to allow higher data transmission over longer channels. In addition, camera and display applications based on D-PHY are seeing adoption in applications beyond mobile, like consumer, computing and multimedia. This presentation illustrates common use cases, and details how MIPI D-PHY can operate at 2.5 Mbps over multiple lanes to enable higher performance. The presentation will also give a brief roadmap of the D-PHY specification.
Raj Kumar Nagpal currently serves as a Senior Staff Engineer in the Synopsys, Inc, Noida, India. He has over 24 years of research and industrial experience in various fields, including Signal integrity, power integrity, High speed links, RF engineering and Product Validations. He currently serves as the Synopsys, Inc. representative in MIPI PHY Working Group while managing the following positions: Chair MIPI D-PHY Sub Group and Vice Chair MIPI PHY Working Group. Prior to joining ST Microelectronics in 2001, he held various R&D positions in several organizations, including Defence Research and Development Organization (DRDO), Central Electronics Limited, Sahibabad, UP, and Scientific Instrument Co. Ltd., Ghaziabad. Mr. Nagpal has also co-authored and published extensively in IEEE conferences.
Abstract: There is a rapid increase in usage of multiple camera system in applications such as drones, automotive, robotics and machine vision. These applications use anywhere from 3 to 12 cameras which capture and process images and many a times also transmit these images real-time. The broad market has been leveraging on the mobile eco-system to design these systems by using application processors, image sensors, peripheral logic and popular camera interface standard such as MIPI CSI-2. In this presentation, Microsemi’s Prem Arora would discuss applications which use multi-cameras and explain how an FPGA-based solution can be used to aggregate the cameras using MIPI CSI-2 interface.
Prem Kumar Arora is the Director of Marketing, SoC and FPGA group at Microsemi. His responsibilities include product management, solutions engineering, eco-system and partner development. Prior to his current role at Microsemi, Prem was the group manager of wireless products at Cypress Semiconductor. Prem holds a BE in Electronics and Communication Engineering and is an alumni of INSEAD.
Abstract: Over the years, a large variety of low-speed I/O interfaces have proliferated in various systems in order to provide critical functionality such as: system configuration, power management, system resets, debug, firmware updates & other low-speed data communications. For example, consider the highest volume mobile system (Ref: MIPI System Diagram) there are about a dozen low-speed interfaces. Typically, these interfaces include multiple instances I2C, SPI, UART, SPMI and 1-wire.
As the bandwidth requirement is small, these wires carry disproportionately higher cost per bandwidth compared to higher speed interfaces, say, based on D-PHY and PCI-Express. As the mobile components are being adopted in emerging mobile-influenced applications like drones, AR/VR, and automotive, these slow-speed interfaces tend to add non-trivial system cost, especially, if these have to be extended over longer distances and/or through connectors or hinges.
In this presentation, we will address how to aggregate multiple slower-speed interfaces over one or two wires by using ultra-low power and small size mobile FPGAs. We will show that one or two wires running at speeds up to 100Mbps can carry the traffic associated with many of these interfaces as well as various GPIOs. We will discuss the tradeoffs involved among multiple requirements which include bandwidth, latency, number and types of interfaces, SW drivers and platform support.
Satwant Singh is the Senior Director of Strategic Planning at Lattice Semiconductor, where he is responsible for ecosystem involvement for new developments and Lattice’s product capabilities roadmaps. Singh serves as the Vice Chair of MIPI Alliance’s RIO Working Group, as well as for the MIPI Sensor Working Group focused on developing new I3C interface specification. Singh holds a master’s of science in Electrical Engineering from the University of Toronto and has more than 30 patents.
Abstract: Low-cost and low-power FPGAs with CSI2/DSI interfaces have been enabling customers to leverage mobile image sensors, displays and processors for innovative applications in mobile-influenced markets, including consumer, medical, industrial, and automotive. This presentation will highlight the evolution of these types of applications, including the unique issues faced by system and software developers in mobile-influenced markets. Most mobile components are designed for specific use cases such as smartphones, tablets and laptops. As such, the mobile system integration is generally straightforward. However, for innovative mobile-influenced applications (i.e., AR/VR and drones), the mobile components don’t always fit together nicely. For example, a drone might need many more cameras than can be directly accommodated by the mobile application processors (APs). In addition, these cameras have different resolutions and frame rates, e.g., high-frame rate and resolution for videography, and lower resolution for collision avoidance. Within these mobile-influenced use cases, there are common trends such as interfacing of consumer, industrial and automotive grade image sensors to a mobile AP, synchronizing and aggregating multiple image sensors, interfacing to multiple displays, multiplexing between display sources, and interfacing to specialty displays. Connectivity and some video processing through programmable FPGAs often aid in the development of these systems, where the functionality was unforeseen or previously couldn’t be realized. Examples of end applications and extrapolated architectural trends for several use cases will also be explored.
Tom Watzka is the Technical Mobile Solutions Architect at Lattice Semiconductor with over 20 years of experience in developing embedded products, including 7 years developing consumer mobile solutions. Currently, Watzka is the Marketing Product Manager for the CrossLink video bridge product line, focused on mobile and mobile influenced markets. He received his BS degree from the Rochester Institute of Technology, MS degree from Pennsylvania State University, and conducted his Master’s Thesis on FFT algorithms.
Abstract: By using RMMI interface as the standard Interface we can do 100% functional validation when compared with functional verification. By using this technique the dependency on physical layers can be by-passed during initial stages of RTL or FW development. The only challenge here is to develop simple hardware connecting parallel lines of Host to DUT for RMMI interface. This method can be used to run regression’s on Emulation platform which will corner all the DUT RTL and DUT FW issue’s prior to RTL/ROM code freeze. When we run this kind of Emulation platform parallel to Simulation environment it will be an added advantage in identifying critical/corner issue which cannot be covered in Verification flow sometimes. By the time Physical Layer (Analog Block) is stable for Integration we can make sure Digital Block is also ready for RTL freeze. Finally by implementing this idea we can see few bugs in advance.
Sreekanth Varma Dantuluri has been a VLSI/FPGA Engineer at Western Digital since 2014. He received his master’s degree in VLSI from IIIT in 2008. He has been actively participating in MIPI discussion’s and working on MIPI-based solutions for the past 3 years. He is very energetic in debugging MIPI UniPro and MIPI M-PHY related issues.