MIPI Demo Day Taipei 2026
21 October 2026
MIPI I3C Developments and New MIPI Specification for I/Os Over I3C Bridge
Presenters: Eyuel Zewdu Teferi, Aruni Nelson
The first part of this presentation provides an update on the latest developments in MIPI I3C®, covering advanced features such as HDR modes, multilane communication, target reset and I²C backward compatibility. It also previews upcoming I3C v1.3 enhancements, including extended-length buses, multi-bus bridging, data protection and functional safety, highlighting the new applications they enable.
The second part of the presentation introduces the forthcoming MIPI Specification for I/Os Over I3C Bridge. The new specification will standardize the bridging of I²C, SPI, UART and GPIO interfaces over MIPI I3C to reduce pin count, simplify system design, improve interoperability and extend the life of existing peripheral devices. This part concludes with a look ahead at future deliverables from the MIPI I/O Bridges Working Group.
Chair, MIPI I3C Working Group
Chair, MIPI I/O Bridges Working GroupMIPI A-PHY: New Compliance Program and Recent Specification Developments
Presenters: Edo Cohen, Tom Kopf
This presentation provides the latest insights into the MIPI A-PHY® specification and the new MIPI A-PHY Compliance Program, which supports its continued industry adoption. The session begins with an overview of the latest developments in MIPI’s high-speed, long-reach SerDes interface, including the release of A-PHY v2.1. It highlights key advances across the A-PHY ecosystem, including growing industry adoption, strategic collaborations and emerging implementations. Next, the presentation introduces the MIPI A-PHY Compliance Program, explaining its structure, processes and benefits. Learn how transmitter and receiver physical layer testing supports broader industry adoption and enables the reliable, scalable deployment of A-PHY-enabled devices in automotive architectures.
Chair, MIPI A-PHY Compliance Advisory GroupExploring MIPI SWI3S: Features, Applications, Tools and What's Next
Presenter: Aruni Nelson
The MIPI SWI3S® v1.0 specification defines a low-latency, multi-drop audio interconnect with bandwidth up to 76 Mbps, supporting both single-ended and differential-low-voltage signaling modes through a unified protocol and software stack. Designed for applications ranging from compact wearables to automotive and robotics, the specification features low-voltage, embedded-clock signaling for reduced EMI/EMC and long cable support.
This presentation covers SWI3S use cases, architecture, protocols, command flows and key improvements over existing audio interfaces. It also provides an overview of supporting tools such as the SWI3S visualizer and a preview of the forthcoming Audio Bus Controller Interface (ABCI) and planned enhancements expected in SWI3S v1.1.
What's Coming in MIPI DSI-2 v3.0 and DCS v3.0
Presenter: Samson Kim
The upcoming releases of MIPI DSI-2™ v3.0 and MIPI DCS™ v3.0 will introduce new capabilities for next-generation displays, with a focus on low-power operation and emerging AR applications. This session presents the latest enhancements, including partial update in video mode, field-sequential display support, command mode peripheral sync synchronization, frame synchronized single wire peripheral to host (P2H) sideband interface, line group sequential support, multipoint support, and new DCS commands for partially refreshed displays.
The presentation provides insight into the technical motivation, implementation considerations and benefits of these new features, explaining how they can enable more efficient display architectures in preparation for AR- and 6G-ready applications.
